Pipelined Error Correction Decoder for Low-Latency Flash Reads
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Solution Overview
Problem
Flash memory systems with high bit-density single-bit/cell or multi-bit/cell structures face reduced read performance due to increased error rates, requiring more detection and correction steps that hinder system throughput.
Innovation Solution
A memory system with a pipelined error correction decoder architecture that uses dual buffer memories and a multiplexer to simultaneously correct errors in one set of data while detecting errors in another, employing convolutional or BCH decoders to enhance throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high bit-density single-bit/cell or multi-bit/cell structures are used in flash memory, then storage capacity is improved, but error rate increases and read performance deteriorates
Solution Approach 1:
The incoming data stream is divided into multiple sectors, with each sector processed by a dedicated decoding pipeline. The data is segmented into first and second sets that are processed simultaneously in parallel pipelines, allowing high-capacity data to be handled in manageable chunks that can be corrected efficiently.
Solution Approach 2:
Error detection is performed on the second set of data while error correction is being applied to the first set. This preliminary detection prepares the system for subsequent correction operations, ensuring that errors are identified before they propagate through the system.
2Reliability
If more error detection and correction steps are performed to handle high error rates, then reliability is improved, but system throughput decreases
Solution Approach 1:
The dual-pipeline architecture ensures continuous operation by overlapping error detection and correction operations. While the first pipeline corrects errors in the first set of data, the second pipeline simultaneously detects errors in the second set of data, eliminating idle time and maintaining continuous throughput.
Solution Approach 2:
The system dynamically switches between processing different data sets through the multiplexer, which routes data between the two parallel pipelines based on operational stage. This dynamic allocation of processing resources maximizes throughput while ensuring comprehensive error correction.
3Device complexity
If sequential error detection and correction is used in conventional decoders, then device complexity is reduced, but latency increases
Solution Approach 1:
The multiplexer dynamically switches between routing the first set of data to the error corrector and routing the second set of data to the error detector. This dynamic switching enables parallel processing operations that would otherwise require sequential execution, reducing latency without permanently increasing hardware complexity.
Solution Approach 2:
A single error detector and error corrector unit serves multiple functions by processing different data sets at different times. The same hardware resources are universally applied to both error detection and error correction tasks, as well as to multiple data sectors, eliminating the need for separate dedicated hardware for each function.
Data Source
AI summary
A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.