Pipelined FEC Codec Architecture for Low-Latency Check Byte Generation
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Solution Overview
Problem
Current implementations of forward error correction (FEC) codecs for computer buses, such as those using Reed-Solomon codecs and Galois field arithmetic, face challenges in reducing power consumption, complexity, and resource requirements, particularly in high-speed applications like PCIe Gen6 and next-generation interconnects.
Innovation Solution
A flat and pipelined implementation of FEC encoders and decoders utilizing Galois Field (GF) arithmetic is proposed, which reduces area overhead and latency, supporting various link subdivisions and configurations like x16, x8, x4, and x2, by employing a port encoder with Galois field multipliers and adders to generate check bytes efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional Reed-Solomon FEC codec implementations are used, then error correction functionality is provided, but power consumption and complexity are high
Solution Approach 1:
The patent divides the input message into multiple input substrings that are processed in parallel by separate FEC encoders. Each encoder handles a portion of the data independently, reducing the computational burden on any single processing unit while maintaining overall error correction functionality across the entire message.
Solution Approach 2:
The patent transforms the traditional sequential processing approach into a parallel processing architecture by introducing a dimensional change from single-stream to multi-stream processing. Multiple FEC encoders operate simultaneously on different input substrings, effectively adding a parallel processing dimension that reduces overall complexity and power consumption per processing unit.
2Reliability
If traditional FEC encoding methods are used, then check bytes are generated for error correction, but area overhead and latency are increased
Solution Approach 1:
By segmenting the input message into multiple substrings and processing them in parallel, the patent reduces the time required to generate check bytes for the entire message. Each encoder works on a smaller portion simultaneously, eliminating the sequential processing bottleneck present in traditional methods.
Solution Approach 2:
The patent performs preliminary parallel encoding of input substrings before final check byte generation and assembly. This preliminary action allows multiple encoding operations to proceed concurrently, reducing overall latency compared to waiting for sequential processing of each message portion.
3Productivity
If high-speed FEC processing is implemented, then data transmission speed is improved, but resource requirements increase
Solution Approach 1:
The patent segments the high-speed processing task into multiple parallel encoder units, each handling a portion of the data stream. This segmentation allows the system to achieve high overall throughput while each individual unit consumes fewer resources, effectively distributing the resource requirements across multiple smaller processing elements.
Solution Approach 2:
The patent implements a universal FEC encoding architecture where multiple encoders perform the same function on different input substrings. This multi-functional approach allows the system to achieve high processing speeds through parallelism while using identical, optimized resource configurations for each encoder, improving resource utilization efficiency.
Data Source
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AI summary
Embodiments herein describe a FEC codec for generating a check byte for a message. The FEC codec includes a port encoder having a storage unit, a Galois field multiplier, and a sum unit. The storage unit stores a first staged result, which is accumulated based on previous sets of input bytes of the message for all clock cycles from a first clock cycle to a clock cycle immediately prior to the current clock cycle. The Galois field multiplier performs a Galois field multiplication of the first staged result and a power of the alpha to generate a Galois field product. The sum unit performs a Galois field addition on an internal input based on a consolidated byte for the current clock cycle and the Galois field product to generate a second staged result for subsequent use to generate the check byte. Other embodiments may be described and/or claimed.