Pipelined FEC Codec Architecture for Low-Area, Low-Latency Buses
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Solution Overview
Problem
Current forward error correction (FEC) codecs for computer buses face challenges in achieving efficient area and latency reduction, particularly in implementations for next-generation interconnects like Compute Express Link (CXL) and Ultra Path Interconnect (UPI), where existing solutions do not adequately optimize for reduced implementation areas and latency across multiple protocols.
Innovation Solution
The implementation of a flat and pipelined FEC encoder/decoder design utilizing Galois Field arithmetic, which includes a port encoder with a storage unit, Galois field multiplier, and sum unit, generates check bytes by performing Galois field multiplication and addition operations across multiple clock cycles, optimizing area efficiency and latency for PCIe Gen6 and other protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional FEC codec implementations are used, then error correction functionality is provided, but area overhead and latency are excessive for next-generation interconnects
Solution Approach 1:
The patent divides the input message into multiple input substrings that are processed in separate clock cycles. This segmentation allows the FEC encoder to process data in smaller chunks, reducing the required implementation area while maintaining error correction functionality across the entire message.
Solution Approach 2:
The patent transitions from a traditional time-sequential processing approach to a pipelined architecture that processes multiple input substrings across different clock cycles. This dimensional change in processing methodology reduces area overhead by reusing hardware resources across multiple cycles while maintaining throughput.
2Loss of time
If traditional FEC codec implementations are used, then error correction functionality is provided, but latency is excessive for next-generation interconnects
Solution Approach 1:
The patent performs preliminary processing by dividing the input message into substrings and pre-computing check bytes for each substring in advance. This preliminary action reduces the critical path latency during final decoding operations, as the error correction data is already prepared and stored for quick retrieval.
Solution Approach 2:
The patent implements a pipelined architecture where the FEC encoder continuously processes multiple input substrings across different clock cycles without idle periods. This continuity of useful action reduces overall processing latency by eliminating wait states and keeping the hardware resources continuously utilized.
3Area of stationary object
If a pipelined FEC encoder design is implemented across multiple clock cycles, then area overhead is reduced, but processing complexity increases
Solution Approach 1:
The patent uses identical Galois field multiplier and sum unit circuits for processing each input substring across different clock cycles. This copying of the same hardware block reduces design complexity compared to creating unique processing paths for each cycle, while still achieving area reduction through resource sharing.
4Area of stationary object
If check bytes are generated through Galois field multiplication and addition across multiple clock cycles, then area efficiency is improved, but processing time per byte increases
Solution Approach 1:
The patent segments the encoding process into discrete clock cycle operations, where each cycle processes a specific input substring to generate its corresponding check bytes. This segmentation allows parallel processing of multiple substrings across different cycles, maintaining overall throughput while reducing the area required for any single processing stage.
Data Source
AI summary
Embodiments herein describe a FEC codec for generating a check byte for a message. The FEC codec includes a port encoder having a storage unit, a Galois field multiplier, and a sum unit. The storage unit stores a first staged result, which is accumulated based on previous sets of input bytes of the message for all clock cycles from a first clock cycle to a clock cycle immediately prior to the current clock cycle. The Galois field multiplier performs a Galois field multiplication of the first staged result and a power of the alpha to generate a Galois field product. The sum unit performs a Galois field addition on an internal input based on a consolidated byte for the current clock cycle and the Galois field product to generate a second staged result for subsequent use to generate the check byte. Other embodiments may be described and/or claimed.