Pipelined FEC for Vector Signaling With Low-Latency Error Correction
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Solution Overview
Problem
High-speed communications systems face challenges in minimizing error correction latency and power consumption while maintaining low Bit Error Rates (BER) in chip-to-chip communication links with low uncorrected BER, especially with existing Forward Error Correction (FEC) techniques that introduce significant latency and computational power consumption.
Innovation Solution
The implementation of a pipelined Forward Error Correction (FEC) method using vector signaling codes, where error correction syndrome values are incrementally updated as data bits are received, allowing for efficient error detection and correction without the need for long check sequences, thereby reducing latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional Forward Error Correction (FEC) techniques are used for error correction in high-speed communications, then error correction capability is improved, but latency and power consumption increase significantly
Solution Approach 1:
The patent segments the error correction process into incremental updates that occur continuously as data bits are received, rather than waiting for complete codewords. The syndrome values are updated in stages, allowing early error detection and correction to begin before all data is received, thereby reducing overall latency while maintaining correction capability.
Solution Approach 2:
The patent performs preliminary error correction actions by calculating syndrome values incrementally as data arrives. This allows the system to prepare correction information in advance and begin correcting errors before the complete data set is received, reducing the time needed for error correction processing.
2Reliability
If conventional Forward Error Correction (FEC) techniques are used for error correction in high-speed communications, then error correction capability is improved, but power consumption increases significantly
Solution Approach 1:
The patent segments the computationally intensive FEC process into smaller incremental updates that are performed continuously. This allows the system to distribute computational load over time and avoid large bursts of power consumption, while still achieving complete error correction capability when all data is received.
Solution Approach 2:
The patent implements continuous incremental updates of syndrome values as data bits are received, maintaining continuous error correction capability throughout the data reception process. This continuous approach avoids the need for large discrete computational operations that would cause power consumption spikes, while maintaining reliable error correction.
3Measurement precision
If long check sequences are used in FEC for reliable error correction, then error detection accuracy is improved, but latency and processing complexity increase
Solution Approach 1:
The patent segments the check sequence processing into incremental syndrome updates that occur as data bits are received. This segmentation allows the system to maintain accurate error detection capability while avoiding the need to store and process extremely long check sequences simultaneously, thereby reducing processing complexity.
Data Source
AI summary
Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.