Pipelined Digital Filter Across Clock Domains With Shared Operators
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Solution Overview
Problem
Digital signal processing (DSP) technologies face challenges in implementing efficient digital filters with pipeline structures due to high silicon area occupation, leading to cost and performance limitations, especially in applications requiring multiple frequencies and complex operators with memory, such as metrology.
Innovation Solution
The implementation of a digital filter with a pipeline structure utilizing structured clock domains to coordinate different logic structures across various frequency domains, incorporating a re-sampling module, phase generator, and buffer memories to maintain throughput and precision, allowing for the reuse of digital operators across channels and flexible clock management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital filters are implemented with pipeline structures using multiple copies of digital operators, then processing throughput is improved, but silicon area occupation increases
Solution Approach 1:
The patent merges multiple digital operator instances into a single shared operator that processes samples from multiple channels sequentially. The resampling module combines samples from different channels and clock domains into a unified stream that feeds into one operator, eliminating the need for separate operator copies for each channel while maintaining processing throughput.
Solution Approach 2:
The shared digital operator is designed to be universal, capable of processing samples from multiple channels and clock domains. The operator can be dynamically configured to handle different channel combinations, making it multi-functional and replacing what would traditionally require multiple dedicated operators.
2Area of stationary object
If digital operators are re-used across multiple channels with queue schemes, then silicon area is reduced, but settling time increases
Solution Approach 1:
The resampling module performs preliminary actions by pre-processing and reorganizing samples from multiple channels and clock domains before they reach the shared operator. Samples are buffered and reordered in advance, so when the shared operator processes them, the transition between channels is already prepared, minimizing settling time.
Solution Approach 2:
The resampling module acts as an intermediary between the multiple input channels and the shared digital operator. It mediates the data flow by buffering, reordering, and synchronizing samples from different channels and clock domains, allowing the shared operator to switch between channels without requiring full settling time.
3Measurement precision
If multiple digital operators are instantiated for different channels, then processing precision is maintained, but device complexity increases
Solution Approach 1:
The patent segments the processing function into two distinct parts: the resampling module that handles channel multiplexing and clock domain coordination, and the shared digital operator that handles the actual filtering. This segmentation allows precision to be maintained in the operator while complexity is isolated to the resampling control logic.
Solution Approach 2:
The resampling module serves as an intermediary that manages the complexity of handling multiple channels and clock domains, while the shared operator maintains processing precision. The intermediary handles the complex tasks of sampling rate conversion and channel multiplexing, allowing the operator to focus on precise filtering without being burdened by channel management complexity.
Data Source
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Figure 3~5
AI summary
A digital filter with a pipeline structure comprises a plurality of processing structures (10, 12) timed by respective clock signals (CLK10, CLK12). Each structure in turn comprises a number of processing modules (A10, B10, C10, D10; A12, B12, C12, D12) for processing input samples (A1, B1, C1, D1). A phase generator (16; 160 to 168) is provided for aligning the aforesaid processing modules (A10, B10, C10, D10; A12, B12, C12, D12) with the input samples (A1, B1, C1, D1) so that each input sample is processed by respective processing modules (A10, A12; B10, B12; C10, C12; D10, D12) of the processing structures (10, 12). An up-sampling buffer (144) and a down-sampling buffer (142), which can be activated when the processing structures (10, 12) operate at different clock frequencies, so that the digital filter comprises at least one first clock domain (CLK10) and at least one second clock domain (CLK12), convert the signal samples between the first clock domain (CLK10) and the second clock domain (CLK12).