Pipelined Floating Point Acceleration Using Exponent Alignment

The patent segments the floating point addition operation into distinct pipeline stages: exponent comparison, shift amount calculation, mantissa alignment, and result generation. Each stage processes a specific aspect of the operation independently, allowing parallel processing of multiple operands simultaneously. This segmentation enables the system to maintain high productivity while reducing the time each individual operation takes by overlapping execution of different stages.

The patent performs preliminary actions by pre-calculating shift amounts based on exponent differences before the actual addition operation. The exponent comparison and shift amount determination are completed in advance, allowing the mantissa alignment to proceed efficiently. This preliminary preparation reduces the critical path delay and enables faster processing of multiple operands in pipeline fashion.

The patent designs a universal floating point adder structure that can handle multiple operands through pipelining rather than implementing separate adders for each operation. The same hardware resources (comparator, shift calculator, aligner, compressor, adder) are reused across multiple pipeline stages and clock cycles, achieving high processing speed while minimizing device area. This multi-functional approach allows the circuit to process N operands using a constant number of hardware components.

The patent implements dynamic pipelining where data flows through different stages at different times, with control signals dynamically routing operands through the pipeline stages. The shift calculator dynamically calculates shift amounts based on exponent values, and the aligner dynamically shifts mantissas by the calculated amounts. This dynamic operation enables high-speed processing without requiring static duplication of hardware resources.

The patent maintains continuous useful action through pipelined processing where new operands are fed into the exponent comparison stage while previous operands progress through alignment and addition stages. The compressor continuously compresses aligned mantissas, and the adder continuously generates results. This continuous operation achieves high computational throughput without requiring complex simultaneous switching of all operands, as each stage processes data continuously in sequence.

The patent introduces intermediary components that simplify the overall circuit complexity: the shift calculator acts as an intermediary between exponent comparison and mantissa alignment, converting exponent differences into shift amounts. The aligner serves as an intermediary between raw mantissas and the compressor, performing alignment based on shift amounts. These intermediary stages break down the complex task of multi-operand addition into simpler, more manageable sub-tasks that can be implemented with less complex hardware.