Pipelined Galois Counter Mode Hash Circuit for Multi-Channel Encryption
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Solution Overview
Problem
Current integrated circuit systems designed for encryption or decryption face speed and timing closure issues due to the inability to pipeline the critical path in hash calculations, particularly in secure communication devices with multiple channels, leading to inefficiencies in performing authenticated encryption or decryption across a large number of channels.
Innovation Solution
A pipelined Galois counter mode (GCM) hash circuit is developed, where the hash sequence is refactored into independent sequences, each processed in separate pipelines, and the resulting hash values are multiplied in a multi-cycle mode, allowing for efficient pipelining and improved throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate circuits are used for respective channels to ensure security, then security is improved, but device complexity increases and the ability to pipeline hash calculations is lost
Solution Approach 1:
The patent merges multiple separate hash calculation circuits into a single shared circuit that serves multiple channels. The Galois field multiplier and hash calculation logic are consolidated into one resource that is time-multiplexed across different channels, eliminating the need for physically separate circuits for each channel while maintaining security through proper state isolation and sequential processing.
Solution Approach 2:
The patent introduces dynamic pipeline stages that can be configured for different channels at different times. The hash calculation circuit dynamically switches between channels through pipeline stages, allowing the same physical circuit to serve multiple channels with proper timing and state management, thereby reducing device complexity while maintaining security.
2Reliability
If multiple separate circuits are used for respective channels, then security is improved, but speed and timing closure deteriorate due to inability to pipeline
Solution Approach 1:
The patent segments the hash calculation process into multiple pipeline stages, where each stage performs a portion of the Galois field multiplication and hash calculation. This segmentation allows different channels to be processed at different pipeline stages simultaneously, enabling pipelining to improve speed while maintaining security through proper state isolation between channels.
Solution Approach 2:
The patent performs preliminary setup of pipeline registers and state variables before processing each channel's data. By pre-configuring the pipeline stages and initializing states in advance, the system can quickly switch between channels without losing timing closure, thereby improving overall speed while maintaining security.
3Reliability
If hash sequence is processed recursively, then security is maintained, but pipelining capability is lost and productivity decreases
Solution Approach 1:
The patent segments the recursive hash calculation into discrete, non-recursive pipeline stages. Each stage performs a fixed portion of the calculation using pre-computed constants and lookup tables, eliminating the need for recursive operations while maintaining the cryptographic security of the GCM algorithm. This segmentation enables pipelining and significantly improves productivity.
Solution Approach 2:
The patent uses periodic clock cycles to advance different pipeline stages, with each stage performing its operation at regular intervals. This periodic action allows multiple channels to be processed in an interleaved manner through the pipeline, maintaining security while dramatically improving productivity compared to sequential recursive processing.
4Reliability
If 64 or more separate circuits are used for channels, then security is improved, but current FPGAs cannot support such system designs
Solution Approach 1:
The patent merges 64 or more separate channel circuits into a single shared Galois field multiplier and hash calculation circuit. This consolidation reduces the device complexity from requiring 64 separate circuit instances to requiring only one shared circuit with multi-channel support, making the system feasible for current FPGA implementations while maintaining security through proper state management and isolation.
Solution Approach 2:
The patent designs a universal hash calculation circuit that can serve multiple channels (64 or more) through time-multiplexing and configurable pipeline stages. The single circuit is made multi-functional by allowing it to process different channels at different times while maintaining proper state isolation, thereby supporting a large number of channels without requiring proportionally large device complexity.
Data Source
AI summary
Integrated circuits, methods, and circuitry are provided for performing multiplication such as that used in Galois field counter mode (GCM) hash computations. An integrated circuit may include selection circuitry to provide one of several powers of a hash key. A Galois field multiplier may receive the one of the powers of the hash key and a hash sequence and generate one or more values. The Galois field multiplier may include multiple levels of pipeline stages. An adder may receive the one or more values and provide a summation of the one or more values in computing a GCM hash.