Pipelined Hash Table Hybrid RAM CAM Architecture
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Solution Overview
Problem
Current network packet processing solutions face challenges with high latency and power consumption due to the need for substantial content-addressable memory (CAM) architectures to supplement random-access memory (RAM), which results in increased memory overhead and power usage, especially when handling large flow tables required for protocols like MPLS and NAT.
Innovation Solution
The implementation of a pipelined hash table processing system that utilizes the entire capacity of a RAM architecture, reducing memory overhead to less than 1% and minimizing power consumption by efficiently allocating memory and using a combination of RAM and CAM architectures to perform hash functions within a single clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CAM architecture is used for deterministic table structure, then classification latency is reduced, but power consumption and area increase significantly
Solution Approach 1:
The patent combines RAM and CAM architectures into a hybrid system where RAM stores the main flow table entries and CAM provides fast lookup for specific fields. This merging allows the system to achieve low latency comparable to pure CAM while consuming significantly less power than pure CAM architecture.
Solution Approach 2:
The patent segments the flow table into different parts stored in different memory types. The main table is stored in power-efficient RAM, while only the most frequently accessed or critical fields are stored in fast but power-hungry CAM. This segmentation reduces overall power consumption while maintaining fast classification for critical paths.
2Speed
If CAM architecture is used for deterministic table structure, then classification latency is reduced, but area increases significantly
Solution Approach 1:
The patent merges RAM and CAM architectures to create a hybrid memory system. RAM provides large capacity at low area cost, while CAM provides fast access for critical lookups. This combination achieves deterministic low-latency classification without requiring a full CAM architecture, thus reducing the overall area significantly.
Solution Approach 2:
The patent segments the memory architecture into RAM for bulk storage and CAM for fast access paths. By placing only essential lookup data in CAM and the majority of flow table entries in RAM, the system achieves fast classification performance with minimal CAM area, resolving the area-latency tradeoff.
3Use of energy by stationary object
If hash tables are used in RAM architecture, then power consumption is reduced, but memory capacity utilization is limited to 60%
Solution Approach 1:
The patent merges hash table organization with a hybrid RAM-CAM architecture. The hash table is implemented in RAM for power efficiency, while CAM is used to resolve collisions and provide deterministic access. This combination allows the system to utilize 100% of RAM capacity while maintaining low power consumption and avoiding the 60% utilization limit of pure RAM hash tables.
4Quantity of substance
If flow table size is increased to 100K entries, then protocol requirements are met, but memory overhead and power consumption increase
Solution Approach 1:
The patent segments the large 100K-entry flow table into two parts: the majority of entries are stored in power-efficient RAM, while only the most frequently accessed or critical entries are replicated in CAM. This segmentation allows the system to support large flow tables meeting protocol requirements while keeping power consumption low by minimizing the portion of data stored in high-power CAM.
Solution Approach 2:
The patent merges RAM and CAM to create a hierarchical memory structure for the flow table. RAM provides bulk storage for all 100K entries with low power consumption, while CAM provides fast access for hot paths. This hybrid approach enables large flow table support without proportionally increasing power consumption.
Data Source
AI summary
Apparatuses and methods for pipelined hashing are described herein. An example apparatus to perform a pipelined hash function may include a first memory to store a first plurality of bucket records, a second memory to store a second plurality of bucket records, and a hash circuit to receive a key and to perform a pipelined hash function using the key to provide a hash value. The hash circuit further to select a first bucket record of the first plurality of bucket records from the first memory based on a first subset of bits of the hash value. The hash circuit further to provide a location of a particular entry of an entry record of the plurality of entry records based on contents of the first bucket record and a second subset of bits of the hash value.