Pipelined Image Video Accelerator Reducing Power
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Solution Overview
Problem
Conventional image and video processing systems face limitations in flexibility and adaptability to new applications, with pure software approaches consuming more power and having limited performance, while pure hardware accelerators are inflexible and require complex coupling with preprocessing and postprocessing blocks.
Innovation Solution
An integrated embedded image and video accelerator that performs pipelined processing within a single chip, enabling simultaneous transformation and encoding/decoding of video data using a hardware-based system adaptable to various applications, with a flexible JPEG accelerator platform.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a pure software approach is used for image and video processing, then flexibility and adaptability are improved, but power consumption increases and performance is limited
Solution Approach 1:
The system is divided into distinct hardware modules including a processor, image processing unit, and video processing unit, each handling specific functions. This segmentation allows the system to offload computationally intensive tasks from the general-purpose processor to specialized hardware units, reducing overall power consumption while maintaining flexibility through software control of the modular architecture.
Solution Approach 2:
The system employs dynamic configuration where the processor can selectively activate or deactivate specific hardware acceleration units based on the current application requirements. This dynamic approach allows the system to consume only the necessary power for the current task while maintaining the capability to adapt to different applications by enabling or disabling specific processing functions.
2Productivity
If a pure hardware accelerator approach is used, then power consumption is reduced and performance is improved, but flexibility and adaptability to new applications are worsened
Solution Approach 1:
The system implements a universal processor that can execute different software programs to control various hardware acceleration units. The processor serves multiple functions by dynamically configuring the hardware resources based on the required application, allowing the same physical hardware to adapt to new applications through software updates rather than requiring dedicated hardware for each application.
Solution Approach 2:
The system pre-configures hardware acceleration units with the capability to perform multiple types of image and video processing operations. By preparing the hardware with versatile capabilities in advance and using software to direct these pre-configured capabilities to specific tasks, the system achieves both high performance and adaptability without requiring redesign for new applications.
3Use of energy by stationary object
If a pure hardware accelerator approach is used, then power consumption is reduced, but device complexity increases due to complex coupling with preprocessing and postprocessing blocks
Solution Approach 1:
The system merges the processor, image processing unit, and video processing unit into a single integrated system on chip. By combining these components and sharing common resources such as memory interfaces and control logic, the system reduces the overall complexity of coupling between separate preprocessing and postprocessing blocks while maintaining low power consumption through the integrated hardware acceleration architecture.
Data Source
AI summary
A method and system for pipelined processing in an integrated embedded image and video accelerator is described. Aspects of a system for pipelined processing in an integrated embedded image and video accelerator may include circuitry that enables pipeline processing of video data within a single chip, wherein the pipeline processing may further include decoding of a block of video data while simultaneously inverse transforming a previously decoded block of video data. Aspects of the system may also include circuitry that enables transformation, within the single chip, of a block of said video data while simultaneously encoding, within said single chip, a previously transformed block of video data.