Pipelined I/O Synthesis via Ant Colony Optimization
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Solution Overview
Problem
High Level Synthesis (HLS) for digital circuit design faces challenges in achieving optimal throughput due to limitations in existing optimization methods, particularly in frame-based algorithms, which result in low throughput when synthesizing pipelined input/output operations.
Innovation Solution
The method integrates Ant Colony Optimization (ACO) with scheduling and binding algorithms, using a data flow graph to simulate and select hardware component combinations for circuit design, incorporating a virtual cost factor to guide ants and avoid stagnation at local optima, and employing folding transformations to reduce hardware components and interconnection costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If frame-based algorithms are used for HLS synthesis, then the design process is simplified, but throughput is reduced
Solution Approach 1:
The patent segments the frame-based processing into multiple pipelined stages, where each stage processes a portion of the frame data. This allows overlapping execution of different frame processing operations, thereby increasing throughput while maintaining the simplicity of frame-based algorithms.
Solution Approach 2:
The patent implements periodic action by introducing pipelined input/output operations that process frame data in periodic cycles. Multiple frames are processed in an interleaved manner across different pipeline stages, enabling continuous data flow and improved throughput compared to sequential frame processing.
2Power
If more hardware components are allocated to operations, then processing capability is improved, but resource usage and cost increase
Solution Approach 1:
The patent applies universality by designing hardware components that can perform multiple functions across different pipeline stages. The same hardware units are reused for processing different frames and different operations within frames, reducing the total quantity of hardware resources needed while maintaining high processing capability.
Solution Approach 2:
The patent introduces dynamic resource allocation where hardware components are dynamically assigned to different operations based on pipeline stage requirements. This dynamic sharing of resources allows the system to achieve high processing capability without permanently allocating excessive hardware resources.
Data Source
AI summary
A method and apparatus for synthesizing pipelined input/output in a circuit design from high level synthesis is described. In one example, an operation is selected to be performed by a circuit, the operation including a plurality of partial operations of different types. The partial operations are ordered based on the ordering of the variables. A plurality of hardware components for performing the operations are represented with a data flow graph having edges and nodes, the edges and nodes being connected based on the ordering of partial operations. A plurality of solutions are simulated for performing the operations as hardware component combinations represented as paths on the data flow graph. For each solution, a cost including a number of edges and nodes traversed on the data flow graph is determined, and a solution is selected with the lowest cost as a hardware component combination for a circuit.