Pipelined MAC Circuitry With Adjustable Concatenation Length
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Solution Overview
Problem
Existing technologies face challenges in efficiently performing multiply and accumulate operations in a pipelined and concatenated manner, particularly in integrated circuits like FPGAs, which require flexible configuration to meet temporal-based system requirements.
Innovation Solution
The implementation of a multiplier-accumulator circuitry in integrated circuits, including a plurality of separate multiplier-accumulator circuits and shadow registers, facilitates pipelining and concatenation of multiply and accumulate operations. This circuitry is organized into rows and connected via a switch interconnect network, allowing for dynamic adjustment of the concatenation length to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple multiplier-accumulator circuits are interconnected in concatenation architecture to perform operations faster, then productivity is improved, but device complexity increases
Solution Approach 1:
The system divides the multiplier-accumulator functionality into multiple separate MAC circuits (first MAC circuit, second MAC circuit, etc.) that can be independently configured and interconnected. Each MAC circuit contains its own multiplier, accumulator, and associated registers, allowing the system to segment the computational workload across multiple units while maintaining individual circuit simplicity
Solution Approach 2:
The system employs dynamic reconfiguration capability where the interconnection between MAC circuits can be changed during operation or between operations. The concatenation architecture allows MAC circuits to be dynamically connected in series for high-speed operations or reconfigured for other purposes, providing adaptability that manages complexity through flexible control rather than fixed complex wiring
Solution Approach 3:
Each MAC circuit is designed as a universal building block that can function independently or be interconnected with other MAC circuits. The circuits can perform multiply-accumulate operations individually or be concatenated to perform longer sequences of operations, allowing the same hardware structure to serve multiple functional requirements and reducing overall system complexity through standardization
2Productivity
If the concatenation length is increased to improve performance, then productivity is improved, but ease of operation deteriorates
Solution Approach 1:
The system provides dynamic control over the concatenation length, allowing the number of interconnected MAC circuits to be adjusted based on performance requirements. Control logic enables the system to configure the interconnection length dynamically, making it easy to adapt to different operational demands without permanent complex wiring arrangements
Solution Approach 2:
The concatenation architecture is segmented into discrete, controllable stages where each MAC circuit represents a manageable unit. This segmentation allows the system to adjust the effective concatenation length by enabling or disabling specific circuit stages, simplifying the operation of configuring performance parameters
Data Source
AI summary
An integrated circuit comprising a plurality of MACs, connected to form a pipeline, to perform a plurality of multiply and accumulate operations, wherein each MAC includes: (A) a multiplier, coupled to memory to (i) receive the multiplier weight data, (ii) multiply first data and the multiplier weight data and (iii) output product data, (B) an accumulator, coupled to the multiplier of the MAC, to add second data and the first product data and output sum data, and (C) a load-store register, coupled to: (i) an output of the accumulator of the associated MAC and (ii) an input of the load-store register of an immediately successive MAC. Each load-store register may include two interconnected registers, and is configurable to, on the same clock cycle, (a) load the initialization data into the accumulator of the immediately successive MAC and (b) store the sum data from the associated MAC into the load-store register.