Pipelined MAC Circuit Chain With Flexible Concatenation Length
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Solution Overview
Problem
Existing multiplier-accumulator circuitry and integrated circuits face challenges in efficiently performing multiply and accumulate operations due to limitations in pipelining and concatenation architectures, which affect system performance and adaptability to temporal-based requirements.
Innovation Solution
The implementation of a plurality of separate multiplier-accumulator circuits with shadow registers and a switch interconnect network that allows for flexible configuration and adjustment of the concatenation length, enabling pipelining and concatenation of operations to enhance performance and adaptability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple multiplier-accumulator circuits are interconnected in concatenation architecture, then the speed of performing multiply and accumulate operations is improved, but the device complexity increases
Solution Approach 1:
The system divides the multiplier-accumulator functionality into multiple separate MAC circuits (first MAC circuit, second MAC circuit, etc.) that can be independently configured and interconnected. Each MAC circuit contains its own multiplier, accumulator, and associated registers, allowing the system to segment the computational workload across multiple units while maintaining individual circuit simplicity
Solution Approach 2:
The concatenation architecture allows dynamic reconfiguration of the system. The plurality of MAC circuits can be selectively interconnected in different configurations depending on the computational requirements, enabling the system to adapt the degree of concatenation (number of MAC circuits used) to balance between speed improvement and complexity management
2Productivity
If the concatenation length is increased to meet temporal-based requirements, then the productivity is improved, but the device complexity increases
Solution Approach 1:
Each MAC circuit is designed with universal functionality to perform both multiplication and accumulation operations, and can serve multiple purposes depending on the configuration. The same MAC circuit can be used in different concatenation lengths or even standalone, providing multi-functionality that improves productivity without requiring additional specialized circuits for each configuration
Solution Approach 2:
The system enables dynamic adjustment of the concatenation length by selectively enabling or disabling interconnections between MAC circuits. This allows the productivity to be scaled by adjusting the number of active MAC circuits in the concatenation chain, while the underlying hardware remains the same, avoiding the need to permanently increase device complexity
3Speed
If shadow registers are added to facilitate pipelining, then the speed of operations is improved, but the device complexity increases
Solution Approach 1:
Shadow registers are implemented to hold input data and intermediate results in advance of the actual computation cycle. The first and second shadow registers store operands before they are processed by the multipliers, allowing the pipeline to be pre-filled and enabling continuous operation without waiting for data preparation, thus improving speed while using simple register structures
4Adaptability or versatility
If flexible configuration options are provided for concatenation, then the adaptability is improved, but the device complexity increases
Solution Approach 1:
The MAC circuits are designed with universal interfaces and control logic that allow them to function in various configurations (standalone, paired, or in longer chains). The same basic control signals and data paths can accommodate different concatenation lengths, providing adaptability without requiring separate control logic for each configuration scenario
Data Source
AI summary
An integrated circuit comprising a plurality of multiplier-accumulator circuits, connected in series, wherein the plurality of multiplier-accumulator circuits includes a first MAC circuit, including a multiplier to multiply first data and first multiplier weight data and output first product data, and an accumulator, coupled to the multiplier of the first MAC circuit, to add second data and the first product data and output first sum data. The plurality of multiplier-accumulator circuits further includes a second MAC circuit including a multiplier to multiply third data and second multiplier weight data and output second product data, and an accumulator, coupled to the multiplier of the second MAC circuit and the accumulator of the first MAC circuit, to generate and output second sum data. A first load-store register is coupled to an output of the accumulator of the first MAC circuit and an input of the accumulator of the second MAC circuit.


