Pipelined Modular Hardware for Variable Bit Width Scalar Multiplication
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Solution Overview
Problem
Existing modular arithmetic logic units in computer systems are limited by their fixed size, which restricts the data they can accommodate, hindering efficient performance in elliptic curve cryptography operations, particularly in scalar multiplications where operands often have different bit widths.
Innovation Solution
A modular hardware block is designed with three multiplication accumulators in series, accompanied by a correction block, to accommodate operands of varying bit widths by modifying them to match the fixed bit width of the hardware block, ensuring efficient processing through heavy pipelining between field operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If modular arithmetic logic units are designed with fixed size, then hardware simplicity is maintained, but the data bit width accommodation is limited
Solution Approach 1:
The patent divides operands of varying bit widths into fixed-size segments that match the hardware block's bit width capacity. Each segment is processed separately through the modular hardware block, allowing the fixed-size hardware to handle variable-size data by breaking it down into manageable chunks.
Solution Approach 2:
The patent introduces a temporal dimension through pipelining, where multiple segments of data are processed in overlapping time intervals. This allows the fixed-bit-width hardware block to efficiently process variable-bit-width operands by distributing segments across multiple clock cycles without requiring additional hardware resources.
2Adaptability or versatility
If modular hardware block processes different bit widths, then versatility improves, but processing time increases
Solution Approach 1:
The patent performs preliminary segmentation of operands into fixed-bit-width segments before processing. This pre-processing step organizes the data in advance, allowing the hardware block to process each segment immediately without waiting for bit width adjustments during computation, thereby minimizing processing time.
Solution Approach 2:
The patent implements heavy pipelining that maintains continuous processing by overlapping the execution of multiple operations. While one segment is being processed, the next segment is being prepared, ensuring that the hardware block is continuously productive and minimizing idle time between operations.
3Productivity
If heavy pipelining is implemented, then processing speed improves, but hardware complexity increases
Solution Approach 1:
The patent designs the modular hardware block to perform multiple functions: segmentation, pipelined processing, and correction operations all within the same fixed-bit-width unit. This universal design allows the same hardware structure to handle various operations without requiring separate dedicated circuits for each function, thereby limiting the increase in hardware complexity.
Solution Approach 2:
The patent changes the operational parameters of the hardware block dynamically based on the input data characteristics. By adjusting the segmentation strategy and pipeline control signals according to the operand bit width, the system achieves high processing speed without requiring physically reconfigurable hardware, thus avoiding excessive complexity.
Data Source
AI summary
Embodiments are directed to elliptic curve cryptography scalar multiplications in a generic field with heavy pipelining between field operations. A bit width is determined of operands in data to be processed by a modular hardware block. It is checked whether the bit width of the operands matches a fixed bit width of the modular hardware block. In response to there being a match, the modular hardware block processes the operands. In response to there being a mismatch, the operands are modified to be accommodated by the fixed bit width of the modular hardware block.