Pipelined Memory Access with ECC for MRAM Reliability
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Solution Overview
Problem
Resistance-change type memory devices, such as MRAM, ReRAM, and PCM, face challenges in ensuring reliable data storage and retrieval due to the need for precise control of voltage and current, which can lead to write errors, read errors, and data corruption, necessitating the use of error correction codes to improve operation reliability.
Innovation Solution
A memory device with an ECC circuit that generates correction codes and detects errors through a pipeline operation involving read, ECC, wait, and write cycles, allowing for parallel execution of data write-back cycles and reducing bus contention, thereby enhancing operation speed and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction code is used to improve operation reliability, then data storage reliability is improved, but processing time and complexity increase
Solution Approach 1:
The memory access operation is divided into multiple pipeline stages (read cycle, ECC cycle, wait cycle, write cycle) that can execute simultaneously. The ECC circuit operates in parallel with memory read/write operations, segmenting the error correction process from the main data access path to avoid sequential delays.
Solution Approach 2:
The ECC circuit performs error correction processing in advance during the ECC cycle before data is written back to memory. By pre-processing error correction during the wait cycle and overlapping it with other pipeline stages, the system prepares corrected data ready for immediate write-back without adding delay to the critical data access path.
2Productivity
If pipeline operation is implemented to improve processing speed, then operation speed is improved, but bus contention increases
Solution Approach 1:
The pipeline operation segments memory access into distinct cycles (read, ECC, wait, write) with dedicated time slots. By dividing the operation into discrete stages with clear boundaries, the system manages bus usage efficiently, allowing different pipeline stages to access the bus at different times without conflict.
Solution Approach 2:
The pipeline operation uses periodic cycles with fixed durations for each stage (read cycle, ECC cycle, wait cycle, write cycle). This periodic structure creates a rhythmic pattern of bus access that prevents contention by ensuring that bus-intensive operations are spaced out in time, with non-bus-intensive ECC processing filling the gaps.
3Object-generated harmful factors
If parallel execution of pipeline stages is implemented to reduce bus contention, then bus contention is reduced, but control complexity increases
Solution Approach 1:
The control system dynamically manages the pipeline stages by enabling parallel execution when resources are available and inserting wait cycles when conflicts arise. The controller adapts the timing and synchronization of different pipeline stages based on real-time bus availability and data readiness, optimizing parallelism while maintaining correctness.
Solution Approach 2:
The wait cycle acts as an intermediary buffer between the read cycle and write cycle, allowing the ECC circuit to process data independently without directly conflicting with memory bus operations. This intermediary stage decouples the data path from the correction path, simplifying control logic by providing natural synchronization points.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution improves the operation reliability of resistance-change type memory devices by enabling parallel execution of pipeline stages, reducing bus contention, and ensuring consistent operation cycles, thus enhancing the reliability of data storage and retrieval.
Implementation Method 1
The MTJ stores data by a tunnel magnetoresistive effect in which magnitude of the resistance in a current path passing through the MTJ is different depending on two states, that is, whether a magnetization state of the free layer is parallel or antiparallel to a magnetization direction of the fixed layer
Implementation Method 2
Rewriting of data is performed by a spin-transfer-torque (STT) method in which electron spin torque is applied to the free layer to cause magnetization reversal
Implementation Method 3
by applying a voltage to this metal oxide film, metal ions are deposited as filaments, and a conduction path is generated in the oxide film
Implementation Method 4
a resistance change layer (for example, chalcogenide) can be rapidly heated and cooled to change the resistance change layer from a crystalline phase to an amorphous phase
Data Source
AI summary
A memory device includes: a memory cell capable of holding data; and an ECC circuit capable of generating a correction code and detecting an error based on the correction code. The memory cell is accessed by a pipeline operation. The pipeline operation includes at least four pipeline stages including a read cycle reading data from the memory cell, an ECC cycle executing generation of the correction code or error detection for the memory cell in the ECC circuit, a wait cycle during which processing for data related to the memory cell is not executed, and a write cycle writing data into the memory cell.