Pipelined MUX Loop Decoupling in Parallel Decision Feedback Circuits
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Solution Overview
Problem
The latency of block decision feedback loops in parallel processing decision feedback circuits limits both the operating clock frequency and block size, restricting the speed and throughput of communication systems.
Innovation Solution
The method involves pre-computing input signal vectors and using pipelined and decoupled decision feedback stages to eliminate intra-clock-cycle dependency, allowing for increased clock frequency and block size by separating and processing intra-block and inter-block dependencies independently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a block decision feedback MUX loop is used to pre-compute and select decision values, then the system can process data in parallel, but the latency of the loop limits the operating clock frequency and block size
Solution Approach 1:
The patent segments the block decision feedback MUX loop into multiple independent MUX chains, where each chain processes a subset of branches. This segmentation allows parallel execution of multiple chains simultaneously, reducing the overall loop latency while maintaining parallel processing throughput.
Solution Approach 2:
The patent introduces a new dimension of parallelism by organizing MUXs into multiple chains that can be executed concurrently. Instead of a single sequential MUX loop, the system creates multiple independent execution paths (chains) that operate in parallel, effectively adding a temporal dimension to the processing architecture.
2Productivity
If the block size is increased to improve throughput, then more data can be processed in parallel, but the loop latency increases proportionally
Solution Approach 1:
By segmenting the MUX loop into multiple chains, the patent enables large block sizes to be processed without proportionally increasing loop latency. Each chain handles a portion of the block, and multiple chains execute in parallel, so the effective latency remains bounded while throughput scales with block size.
Solution Approach 2:
The patent performs preliminary organization of MUXs into chains before processing begins. This pre-configuration allows the system to handle large blocks of data by distributing them across multiple prepared chains, enabling scalable throughput without linearly increasing critical path latency.
3Speed
If the clock frequency is increased to improve speed, then processing is faster, but the loop latency becomes a larger fraction of the clock period
Solution Approach 1:
Segmenting the MUX loop into multiple chains reduces the critical path latency within each chain. This allows the system to operate at higher clock frequencies because the shortened loop latency becomes a smaller fraction of the clock period, improving overall processing speed.
4Device complexity
If series-connected MUXs are used to implement decision feedback, then the circuit structure is simple, but the critical path becomes timing-critical
Solution Approach 1:
The patent segments the series-connected MUX structure into multiple parallel chains. While each chain maintains relative simplicity, the parallel chain structure eliminates the single long critical path, distributing the timing requirements across multiple shorter paths and improving timing reliability.
Solution Approach 2:
By transitioning from a single-series MUX path to multiple parallel chains, the patent adds a spatial dimension to the circuit architecture. This dimensional change transforms the timing-critical single path into multiple less-critical parallel paths, improving timing margins while maintaining structural simplicity.
Data Source
AI summary
This invention discloses circuit and methods to decouple and pipeline block decision feedback multiplexer (MUX) loop in parallel processing decision feedback circuits. In one embodiment of this invention, a block decision feedback MUX loop consists of a pipelined intra-block decision feedback MUX stage and an inter-block decision feedback MUX stage to handle intra-block decision feedback selection and inter-block decision feedback selection separately. In the pipelined intra-block decision feedback stage, inter-block dependency is eliminated to enable pipelining. In another embodiment of this invention for moderately timing-critical parallel processing decision feedback circuits, a block decision feedback MUX loop is piecewise split into multiple series connected segments that each segment contains parallel branches. The intra-segment decision feedback selections of different segments are decoupled and processed in parallel. The selections of final decision signals of different branches in a segment are parallelized.