Pipelined Phase Rotator Architecture for Low-Jitter 200-Gb/s CDR
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Solution Overview
Problem
Existing data center communication hardware faces challenges in reducing power consumption while meeting increasing bandwidth demands, particularly in high-speed wireline transceivers where stringent jitter requirements are difficult to meet with traditional Phase Rotators (PRs).
Innovation Solution
The implementation of pipelined phase rotators combined with twin PRs and Finite Impulse Response (FIR) filters in a Clock-and-Data Recovery (CDR) loop, which reduces power and area consumption while improving jitter performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional Phase Rotators are used in high-speed wireline transceivers, then bandwidth demand can be met, but power consumption increases and jitter requirements are difficult to meet
Solution Approach 1:
The phase rotator is divided into multiple pipeline stages, where each stage processes a portion of the phase rotation task. This segmentation allows the system to achieve high-speed operation (meeting bandwidth demands) while reducing the power consumption of each individual stage, as the computational load is distributed across multiple smaller units rather than concentrated in a single high-power component.
2Productivity
If traditional Phase Rotators are used in high-speed wireline transceivers, then bandwidth demand can be met, but jitter requirements are difficult to meet
Solution Approach 1:
By segmenting the phase rotator into multiple pipeline stages, each stage can be optimized for specific jitter characteristics. The multi-stage architecture allows for better control and reduction of accumulated jitter compared to a single-stage design, thereby meeting stringent jitter requirements while maintaining high bandwidth capability.
Solution Approach 2:
The patent implements a Clock-and-Data Recovery (CDR) loop that uses feedback mechanisms to monitor and adjust the phase rotation process. This feedback control helps maintain stable operation and reduces jitter by continuously correcting phase errors, enabling the system to meet both high bandwidth and stringent jitter requirements.
3Use of energy by stationary object
If pipelined phase rotators are implemented, then power and area consumption are reduced, but device complexity increases
Solution Approach 1:
The phase rotator is segmented into multiple pipeline stages, each handling a portion of the phase rotation computation. This segmentation reduces the area consumption of each individual stage while distributing the overall complexity across multiple simpler units, achieving a balance between reduced area and manageable device complexity.
Data Source
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AI summary
Aspects of the subject disclosure may include, for example, implementing a first stage including a first number of phase rotators in parallel generating respective clock phases off set by a fixed amount; a second stage including a second number of phase rotators receiving outputs from the first number of phase rotators of the first stage, the second stage outputting a first weighted sum of respective clock phases generated by the second number of phase rotators. The subject disclosure further includes the second number of phase rotators being less than the first number of phase rotators, and a total number of bits dedicated to phase selection being split across the first stage and the second stage. Other embodiments are disclosed.