Pipelined Phase Rotators for Low-Power Clock and Data Alignment

Solution Overview

Problem

Current data center communication hardware faces challenges in reducing power consumption while meeting increasing bandwidth demands, with existing solutions like LC Voltage Controlled Oscillators consuming high power and area, especially in high-speed wireline transceivers.

Innovation Solution

The method involves pipelining phase rotators and using twin phase rotators combined with Finite Impulse Response filters in a Clock-and-Data Recovery loop to achieve low power and area consumption, suppressing phase noise and jitter, enabling the use of phase rotators in 200-Gb/s+ SerDes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If LC Voltage Controlled Oscillators are used for clock and data recovery, then jitter performance is improved, but power consumption and area increase significantly

Engineering Contradiction:

Improvejitter performanceVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The phase rotator is divided into multiple stages (first stage, second stage, third stage) that process phase adjustment in sequence. This segmentation allows the system to achieve the required jitter performance through cumulative phase correction while using smaller, more power-efficient individual stages compared to a single high-performance VCO.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent replaces the traditional LC Voltage Controlled Oscillator (analog/mechanical system) with a digital phase rotator implementation using combinatorial logic and lookup tables. This substitution eliminates the power-hungry analog components while maintaining jitter performance through digital phase adjustment mechanisms.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If LC Voltage Controlled Oscillators are used for clock and data recovery, then jitter performance is improved, but device area increases

Engineering Contradiction:

Improvejitter performanceVSAvoiddevice area

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The phase rotator is divided into multiple stages (first stage, second stage, third stage) that process phase adjustment in sequence. This segmentation allows the system to achieve the required jitter performance through cumulative phase correction while using smaller, more power-efficient individual stages compared to a single high-performance VCO.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent replaces the traditional LC Voltage Controlled Oscillator (analog/mechanical system) with a digital phase rotator implementation using combinatorial logic and lookup tables. This substitution eliminates the power-hungry analog components while maintaining jitter performance through digital phase adjustment mechanisms.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Speed

If high-speed communication hardware is designed to meet increasing bandwidth demands, then data transmission speed is improved, but power consumption increases

Engineering Contradiction:

Improvedata transmission speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The system uses periodic phase adjustment through the multi-stage phase rotator, where each stage processes phase correction at optimized intervals. This periodic action allows the high-speed SerDes to maintain accurate clock-data alignment without continuous high-power consumption, enabling fast transmission speeds with reduced energy usage.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent replaces the traditional LC Voltage Controlled Oscillator (analog/mechanical system) with a digital phase rotator implementation using combinatorial logic and lookup tables. This substitution eliminates the power-hungry analog components while maintaining jitter performance through digital phase adjustment mechanisms.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS12176908B2Method and apparatus for clock and data alignment that reduces power consumption

Publication Date: 2024.12.24 CIENA CORP

AI summary

Aspects of the subject disclosure may include, for example, implementing a first stage including a first number of phase rotators in parallel generating respective clock phases offset by a fixed amount; a second stage including a second number of phase rotators receiving outputs from the first number of phase rotators of the first stage, the second stage outputting a first weighted sum of respective clock phases generated by the second number of phase rotators. The subject disclosure further includes the second number of phase rotators being less than the first number of phase rotators, and a total number of bits dedicated to phase selection being split across the first stage and the second stage. Other embodiments are disclosed.