Pipelined Reset Signal Distribution for Balanced Core Timing
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Solution Overview
Problem
Existing reset signal technologies, both synchronous and asynchronous, face challenges in providing effective immunity to glitches and ensuring balanced reset timing in power-saving schemes and high-speed circuits, particularly when clock signals are gated or in asynchronous operations.
Innovation Solution
A method and system for generating and synchronously distributing a reset signal through a pipelined reset circuit with programmable delay times, ensuring balanced and glitch-free reset signal distribution to multiple ports of a core circuit, using input and pipelined reset blocks with programmable delay counters and multiplexers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a synchronous reset signal is used to affect flip-flops on the active edge of a clock signal, then immunity to glitches is improved, but power saving capability deteriorates when the clock signal is gated
Solution Approach 1:
The reset distribution is segmented into multiple pipelined reset blocks that are distributed around the periphery of the core circuit. Each block independently processes and distributes reset signals to specific regions, allowing localized reset functionality without requiring a global gated clock signal, thus maintaining glitch immunity while enabling power savings.
Solution Approach 2:
Reset signals are distributed in advance to all pipelined reset blocks before the actual reset operation is needed. The reset circuit pre-establishes the reset signal paths through the pipelined blocks, so when a reset is required, the signal is already positioned and ready to be applied synchronously to flip-flops, eliminating the need for continuous clock gating.
2Speed
If an asynchronous reset signal is used to affect the state of flip-flops without regard to the clock signal, then high speed operation is improved, but immunity to glitches deteriorates causing spurious reset operations
Solution Approach 1:
The system dynamically adapts between synchronous and asynchronous reset modes. The pipelined reset blocks can operate in synchronous mode with respect to local clock domains for glitch immunity, or asynchronously relative to the global clock for high-speed operation. This dynamic flexibility allows the circuit to achieve both high speed and glitch immunity by selecting the appropriate mode based on operational requirements.
3Device complexity
If reset signals are distributed to multiple ports of a core circuit without pipelining, then device complexity is reduced, but reset timing balance deteriorates
Solution Approach 1:
The core circuit is divided into multiple regions, each served by a dedicated pipelined reset block positioned at the periphery. This segmentation allows each block to independently optimize reset signal timing for its local region, achieving balanced reset timing across the entire circuit while maintaining manageable complexity through modular organization.
Solution Approach 2:
The reset distribution architecture transitions from a single-dimensional centralized approach to a multi-dimensional distributed pipelined structure. Pipelined reset blocks are positioned in spatial dimensions around the periphery of the core circuit, creating a two-dimensional distribution network that naturally balances timing across different regions without requiring complex centralized timing control.
Data Source
AI summary
Methods, circuits and systems may operate to generate a reset signal at an input reset block and synchronously distribute the reset signal, via a number of pipelined reset blocks, to multiple ports of a core circuit. The reset signal may be transmitted successively to each of the pipelined reset blocks to provide delayed reset signals having delay times. The delay times may be based on locations of the pipelined reset blocks in the reset circuit. On or more of the delayed reset signals may be programmably coupled to one or more ports of the core circuit. Additional methods, circuits, and systems are disclosed.