Pipelined Row Decoder Topology for Faster Imager Readout
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Solution Overview
Problem
Existing imaging arrays of pixel sensors face limitations in capturing and reading out images quickly due to address settling times and control line charge-up times, which increase with the size of the array, leading to inefficiencies in processing image data from larger numbers of rows and columns.
Innovation Solution
A latched row driver circuit with row enable latches is introduced, allowing pre-selection of rows and simultaneous application of timing pattern control signals during a timing pattern period, reducing latency and enabling multiple rows to be addressed without additional overhead, thus speeding up the readout process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional row driver circuits are used to select and process rows sequentially, then the circuit structure remains simple, but the address settling time and control line charge-up time increase with array size, reducing processing speed
Solution Approach 1:
The patent applies preliminary action by pre-selecting multiple rows using row address latches before the timing pattern is applied. The row address latches store the selected row addresses in advance, allowing the timing pattern generator to operate on multiple rows simultaneously without waiting for sequential address settling, thus reducing the overall processing time and addressing the speed-time contradiction.
2Productivity
If multiple rows are processed sequentially one at a time, then the control logic remains simple, but the total readout time increases with the number of rows
Solution Approach 1:
The patent applies segmentation by dividing the row selection process into independent segments using row address latches for each row. This allows multiple row segments to be prepared and processed in parallel rather than sequentially, increasing productivity by enabling simultaneous timing pattern application to multiple rows while keeping the control logic relatively simple through modular latch structures.
Solution Approach 2:
The patent applies preliminary action by pre-selecting multiple rows using row address latches before the timing pattern is applied. The row address latches store the selected row addresses in advance, allowing the timing pattern generator to operate on multiple rows simultaneously without waiting for sequential address settling, thus reducing the overall processing time and addressing the speed-time contradiction.
3Loss of time
If row addresses are selected and processed immediately without pre-loading, then the control circuitry remains minimal, but latency is introduced due to address settling and control line charge-up times
Solution Approach 1:
The patent applies preliminary action by pre-selecting multiple rows using row address latches before the timing pattern is applied. The row address latches store the selected row addresses in advance, allowing the timing pattern generator to operate on multiple rows simultaneously without waiting for sequential address settling, thus reducing the overall processing time and addressing the speed-time contradiction.
Data Source
AI summary
An imaging array includes a plurality of rows of pixel sensors. A timing pattern generator generates timing pattern control signals and provide the timing pattern control signals to every row in the array. Timing pattern control signals generated during a timing pattern period directed to operate the pixel sensors in a selected row. A latched row driver circuit includes an enable latch in each row of the array responsive to a row address enable signal provided prior to the timing pattern period to gate the timing pattern control signals to the pixel sensors in the selected row at the start of the timing pattern period. A row address generator circuit is coupled to the timing pattern generator and to the enable latches in each row of the array to generate the row address enable signal for each selected row prior to the timing pattern period.