Pipelined-SAR ADC Circuit With Shared Amplifier and Offset Cancellation
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Solution Overview
Problem
Existing analog-to-digital converters (ADCs) face challenges in achieving high speed and low power consumption, with flash ADCs being the fastest but most costly, SAR ADCs being slow, and pipelined ADCs experiencing increased power consumption due to low voltage supplies.
Innovation Solution
The implementation of a time-interleaved pipelined successive approximation register (SAR) ADC circuit with a first stage for coarse conversion, a shared residue amplifier, a second stage for fine conversion, and digital error correction logic, utilizing capacitive digital-to-analog converters (CDACs) and capacitive attenuators to enhance feedback and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If flash ADC architecture is used, then conversion speed is improved, but implementation cost increases
Solution Approach 1:
The ADC is divided into multiple time-interleaved pipelined-SAR ADCs operating in parallel, where each sub-ADC handles a portion of the conversion task. This segmentation enables higher effective conversion speed without requiring a full flash ADC architecture, thus reducing implementation cost while maintaining high speed performance.
Solution Approach 2:
Multiple time-interleaved ADCs operate in alternating time slots to process input signals. By periodically switching between different sub-ADCs, the system achieves higher effective sampling rates and conversion speed without the complexity of simultaneous parallel processing required in flash ADCs.
2Device complexity
If SAR ADC architecture is used, then implementation cost is reduced, but conversion speed deteriorates
Solution Approach 1:
The patent combines pipelined and SAR ADC architectures into a hybrid pipelined-SAR structure. This merging allows the system to achieve both the cost-effectiveness of SAR ADCs and the high-speed performance of pipelined ADCs, resolving the speed limitation of conventional SAR ADCs while maintaining lower implementation costs.
Solution Approach 2:
The conversion process is segmented into multiple stages with different functions (coarse conversion, fine conversion, offset cancellation). Each stage uses optimized circuitry appropriate for its specific task, enabling high-speed operation without requiring the full complexity of a flash ADC, thus maintaining cost-effectiveness.
3Speed
If pipelined ADC architecture is used, then conversion speed is improved, but power consumption increases
Solution Approach 1:
Different stages of the ADC use different circuit configurations optimized for their specific functions. The first stage uses a configuration optimized for coarse conversion with higher speed requirements, while subsequent stages use configurations optimized for fine conversion with lower power consumption. This local optimization resolves the power-speed tradeoff by applying different quality characteristics to different parts of the system.
Solution Approach 2:
The patent employs dynamic parameter changes including variable gain amplification, adjustable sampling rates, and configurable resolution settings. By changing operational parameters based on input signal characteristics and system requirements, the ADC achieves high-speed conversion when needed while consuming less power during normal operation, resolving the power consumption issue of pipelined ADCs.
4Speed
If multiple time-interleaved pipelined-SAR ADCs are used, then conversion speed and power efficiency are improved, but device complexity increases
Solution Approach 1:
The residue amplifier is designed as a shared resource that serves multiple time-interleaved pipelined-SAR ADCs. This multi-functional component reduces the total number of amplifiers required, thereby reducing overall circuit complexity and power consumption while maintaining high conversion speed through time-interleaved operation.
Solution Approach 2:
Multiple functional blocks (coarse conversion, fine conversion, offset cancellation) are merged into a unified time-interleaved architecture with shared resources. This consolidation reduces redundant circuitry and simplifies the overall system while achieving high-speed performance through coordinated operation of the interleaved channels.
Data Source
AI summary
The present invention provides a pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) circuit with decoupled flip-around MDAC, capacitive attenuation solution and self-embedded offset cancellation. The flip-around MDAC architecture is built for low inter-stage gain implementation. A capacitive attenuation solution is provided for minimizing the power dissipation and optimizing conversion speed. The design reuses SAR ADC to perform offset cancellation, which significantly saves calibration area, power and time.