Pipelined SAR ADC Passive Inter-Stage Amplification for Low Noise

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Solution Overview

Problem

Existing pipelined successive-approximation-register analog-to-digital converters (SAR ADCs face challenges in achieving high conversion rates while minimizing power consumption and noise, particularly due to the sensitivity of inter-stage amplifiers to voltage and temperature variations.

Innovation Solution

A pipelined SAR ADC design utilizing fully passive low-noise MOS transistors as inter-stage amplifiers, which toggle between ground and supply voltage, reducing power consumption and noise, and implemented in CMOS technology with charge redistribution SAR ADC stages to minimize active components and noise sensitivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If an operational amplifier is used as inter-stage amplifier, then amplification performance is improved, but power consumption increases significantly

Engineering Contradiction:

Improveamplification performanceVSAvoidpower consumption

Core Design Contradiction:

PowerVSUse of energy by moving object

Solution Approach 1:

The patent replaces the active operational amplifier with a passive capacitor-based amplification mechanism. The inter-stage amplifier consists of a first capacitor connected to the output of the first SAR ADC stage and a second capacitor connected to the input of the second SAR ADC stage, eliminating the need for powered amplification while achieving the required signal level through capacitive coupling and charge transfer.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent extracts and removes the operational amplifier component from the inter-stage amplification path. By taking out the active amplifier element, the design eliminates its associated power consumption while maintaining functionality through the passive capacitor network that transfers charge between stages.

Inventive Principle:

Principle #2Taking out (Extraction)

2Speed

If a dynamic amplifier is used as inter-stage amplifier, then amplification speed is improved, but sensitivity to voltage and temperature variations increases

Engineering Contradiction:

Improveamplification speedVSAvoidsensitivity to voltage and temperature variations

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent substitutes the dynamic amplifier with a static passive capacitor network. This replacement eliminates the active components that exhibit voltage and temperature sensitivity, providing a stable inter-stage coupling mechanism that is insensitive to environmental variations while maintaining fast charge transfer capability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the fundamental operating parameters from active voltage amplification to passive charge transfer. By using capacitors with fixed values rather than active devices with variable parameters, the system achieves insensitivity to voltage and temperature variations while maintaining the necessary speed through optimized capacitor sizing and charge redistribution timing.

Inventive Principle:

Principle #35Parameter changes

3Use of energy by moving object

If no inter-stage amplifier is used, then power consumption is reduced, but noise requirements on the backend become stringent

Engineering Contradiction:

Improvepower consumptionVSAvoidnoise requirements

Core Design Contradiction:

Use of energy by moving objectVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a passive capacitor-based inter-stage coupling mechanism that provides signal level transformation without active amplification. This approach maintains low power consumption while the capacitor network inherently filters high-frequency noise and provides impedance matching that relaxes the noise requirements on the second SAR ADC stage comparator.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution achieves significant reduction in power consumption and noise, maintains high conversion rates, and is robust against temperature and voltage variations, eliminating the need for continuous calibration and reducing circuit complexity.

Implementation Method 1

the one or more MOS transistors provide a fully passive low-power and low-noise amplifier based on switchable gate capacitance, where transfer to or from the amplifier occurs through charge sharing

Methodology Applied

Scientific EffectCharge sharing: Capacitance

Data Source

PatentUS11152949B2Pipelined successive approximation register analog-to-digital converter and method of analog-to-digital conversion

Publication Date: 2021.10.19 INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)

AI summary

A pipelined successive approximation register analog-to-digital converter (2), SAR ADC, comprises a first SAR ADC stage (4); an inter-stage amplifier (6) for amplifying an analog residue from the first SAR ADC stage; and a second SAR ADC stage (8) input from the inter-stage amplifier, wherein the inter-stage amplifier (6) comprises one or more MOS transistors (16, 18), wherein the source and drain terminals of each of the one or more MOS transistors (16, 18) are connected to each other and may be toggled between ground and a supply voltage.