Pipelined SAR ADC Passive Inter-Stage Amplifier for Low-Noise Conversion

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Solution Overview

Problem

Existing pipelined SAR ADCs face challenges in achieving high conversion rates while minimizing power consumption, noise sensitivity, and reducing the need for complex calibration due to inter-stage amplifier variations.

Innovation Solution

A pipelined SAR ADC design utilizing MOS transistors with switchable gate capacitance for inter-stage amplification, providing a fully passive and low-noise amplifier that reduces power consumption and sensitivity to voltage and temperature variations, while maintaining high conversion rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If an operational amplifier is used as inter-stage amplifier, then amplification is achieved, but power consumption increases

Engineering Contradiction:

Improveamplification capabilityVSAvoidpower consumption

Core Design Contradiction:

PowerVSUse of energy by moving object

Solution Approach 1:

The patent replaces the active operational amplifier with a passive capacitor-based amplifier. The inter-stage amplification is achieved through capacitive coupling and charge redistribution rather than active amplification, eliminating the need for continuous power supply to the amplifier stage while maintaining the required gain.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The amplifier operates in a periodic manner, using clocked switching to transfer and amplify signals only when needed, rather than continuously amplifying as an operational amplifier would. This periodic operation significantly reduces average power consumption.

Inventive Principle:

Principle #19Periodic action

2Power

If a dynamic amplifier is used as inter-stage amplifier, then amplification is achieved, but sensitivity to voltage and temperature variations increases

Engineering Contradiction:

Improveamplification capabilityVSAvoidsensitivity to voltage and temperature variations

Core Design Contradiction:

PowerVSReliability

Solution Approach 1:

The patent replaces the voltage-dependent dynamic amplifier with a passive capacitor-based system. Since capacitors are voltage-independent passive components, the amplification mechanism becomes insensitive to supply voltage variations and temperature drift, improving reliability without requiring calibration.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Use of energy by moving object

If no inter-stage amplifier is used, then power consumption is reduced, but noise requirements on the backend become stringent

Engineering Contradiction:

Improvepower consumptionVSAvoidnoise sensitivity

Core Design Contradiction:

Use of energy by moving objectVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a passive capacitor-based amplifier as an intermediary stage between the first and second SAR ADC stages. This intermediary provides the necessary signal amplification to meet the noise requirements of the backend while maintaining low power consumption, as capacitors can be made with very low loss.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Reliability

If background calibration is implemented to adjust gain, then amplifier sensitivity is reduced, but circuit complexity and power requirements increase

Engineering Contradiction:

Improveamplifier stabilityVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent eliminates the need for background calibration by replacing the active dynamic amplifier with a passive capacitor-based amplifier. The passive nature of capacitors inherently provides stability against voltage and temperature variations, removing the requirement for complex calibration circuits and reducing overall system complexity.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design achieves significant power reduction, improved robustness against temperature and voltage variations, and reduced noise sensitivity, while maintaining high conversion rates and linearity, without the need for complex calibration.

Implementation Method 1

The one or more MOS transistors provide a fully passive low-power and low-noise amplifier based on switchable gate capacitance, where transfer to or from the amplifier occurs through charge sharing.

Methodology Applied

Scientific EffectCapacitance: Capacitance

Data Source

PatentEP3796560B1Pipelined successive approximation register analog-to-digital converter and method of analog-to-digital conversion

Publication Date: 2025.06.25 INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)

Figure 1
Figure 2
Figure 3a~3b

AI summary

A pipelined successive approximation register analog-to-digital converter (2), SAR ADC, comprises a first SAR ADC stage (4); an inter-stage amplifier (6) for amplifying an analog residue from the first SAR ADC stage; and a second SAR ADC stage (8) input from the inter-stage amplifier, wherein the inter-stage amplifier (6) comprises one or more MOS transistors (16, 18), wherein the source and drain terminals of each of the one or more MOS transistors (16, 18) are connected to each other and may be toggled between ground and a supply voltage.