Pipelined SAR ADC Using Residue Voltage-to-Time Conversion
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Solution Overview
Problem
Traditional successive-approximation-register (SAR) analog-to-digital converters (ADCs) face challenges in power efficiency and scalability as they use high gain amplifiers that consume large amounts of power, making them unsuitable for emerging technology nodes like 16 nm or 10 nm minimum feature sizes.
Innovation Solution
A hybrid SAR-ADC that combines voltage-based signal processing to determine most significant bits (MSBs) and time-based signal processing to determine least significant bits (LSBs), utilizing a voltage-to-time conversion element to convert residue voltage into a time domain representation, allowing for low power consumption and compact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional SAR-ADC uses high gain amplifiers to achieve high resolution, then measurement precision is improved, but power consumption increases and device becomes unsuitable for emerging technology nodes
Solution Approach 1:
The patent divides the ADC conversion process into two separate stages: a first SAR-ADC stage that handles most significant bits (MSBs) and a second SAR-ADC stage that handles least significant bits (LSBs). This segmentation allows each stage to operate with lower gain requirements, reducing power consumption while maintaining overall high resolution. The residue from the first stage is processed by the second stage, enabling progressive refinement without requiring a single high-power amplifier.
Solution Approach 2:
The patent implements dynamic element matching (DEM) techniques where capacitor arrays are dynamically switched and reconfigured during the conversion process. This dynamic operation allows the system to maintain high precision across varying input ranges while optimizing power consumption by activating only the necessary capacitive elements for each conversion cycle, rather than maintaining static high-gain amplification throughout.
2Measurement precision
If traditional SAR-ADC uses high gain amplifiers to achieve high resolution, then measurement precision is improved, but device complexity increases making it unsuitable for 16 nm or 10 nm technology nodes
Solution Approach 1:
The patent divides the ADC conversion process into two separate stages: a first SAR-ADC stage that handles most significant bits (MSBs) and a second SAR-ADC stage that handles least significant bits (LSBs). This segmentation allows each stage to operate with lower gain requirements, reducing power consumption while maintaining overall high resolution. The residue from the first stage is processed by the second stage, enabling progressive refinement without requiring a single high-power amplifier.
Solution Approach 2:
The patent implements dynamic element matching (DEM) techniques where capacitor arrays are dynamically switched and reconfigured during the conversion process. This dynamic operation allows the system to maintain high precision across varying input ranges while optimizing power consumption by activating only the necessary capacitive elements for each conversion cycle, rather than maintaining static high-gain amplification throughout.
3Use of energy by moving object
If hybrid SAR-ADC uses voltage-based signal processing for MSBs and time-based signal processing for LSBs, then power consumption is reduced, but device complexity increases due to multiple conversion elements
Solution Approach 1:
The patent divides the ADC conversion process into two separate stages: a first SAR-ADC stage that handles most significant bits (MSBs) and a second SAR-ADC stage that handles least significant bits (LSBs). This segmentation allows each stage to operate with lower gain requirements, reducing power consumption while maintaining overall high resolution. The residue from the first stage is processed by the second stage, enabling progressive refinement without requiring a single high-power amplifier.
Solution Approach 2:
The patent employs a unified capacitive digital-to-analog converter (CDAC) structure that serves multiple functions across both conversion stages. The same capacitive array is reused and reconfigured for both the first and second SAR-ADC stages, reducing the need for separate dedicated components and thereby limiting the increase in device complexity despite the hybrid architecture.
Data Source
AI summary
An analog-to-digital converter (ADC) is disclosed. The ADC includes a successive approximation register and a voltage-to-time conversion element. The successive approximation register is configured to receive an input signal and to generate a first digital signal and a residue voltage. The voltage-to-time conversion element is configured to convert the residue voltage to a time domain representation. The voltage-to-time conversion element includes an amplifier having an input coupled to an output of the successive approximation register and configured to receive the residue voltage, and a zero crossing detector directly coupled to an output of the amplifier. A time-to-digital converter is coupled to an output of the zero crossing detector and is configured to generate a second digital signal.