Pipelined SAR Time-to-Digital Converter for Fast Low-Power Conversion
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Solution Overview
Problem
High-speed data converters face challenges in achieving both high speed and energy efficiency, as boosting converter speed often requires sacrificing energy efficiency, and existing solutions like flash architectures and successive approximation converters suffer from poor power management and noise regulation, especially in time-interleaved SAR ADC architectures.
Innovation Solution
The design combines the energy efficiency of successive approximation converters with the high speed of pipelined converters by using time-domain signaling and digital AND/OR gates to identify early and late edges of clock signals, eliminating the need for comparator decisions in the signal path and implementing a modular digital reference voltage generator with low dropout circuitry for capacitive DACs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If flash architecture is used to achieve high conversion speed, then speed is improved, but power consumption increases proportionally to 2^N
Solution Approach 1:
The conversion process is divided into multiple pipelined stages, each handling a portion of the conversion. This allows parallel processing of different signal components, achieving high speed without requiring all 2^N comparators to operate simultaneously, thus reducing power consumption while maintaining throughput.
Solution Approach 2:
The converter uses periodic sampling and staged conversion cycles where different signal paths are activated at different times. This time-division approach allows the system to achieve high effective conversion speed through parallel staging while each individual stage operates at lower power levels.
2Use of energy by moving object
If successive approximation converters are used to reduce power consumption, then power efficiency is improved, but conversion time increases by a factor of N due to iterative feedback loop
Solution Approach 1:
The successive approximation process is segmented into multiple independent parallel stages, each performing a portion of the bit resolution. By dividing the N-bit conversion into smaller parallel sub-conversions, the total conversion time is reduced from O(N) to O(log N) or constant time per stage, while each stage maintains linear power scaling.
Solution Approach 2:
The converter employs periodic pipelined operation where different stages process different signal components in alternating time slots. This allows overlapping of conversion operations, effectively reducing the average conversion time while maintaining the energy efficiency of successive approximation methods.
3Object-affected harmful factors
If large decoupling capacitance is used to attenuate high-frequency spikes on reference node, then noise regulation is improved, but response time increases due to capacitive load
Solution Approach 1:
The decoupling capacitance is distributed across multiple parallel capacitor banks rather than using a single large capacitor. This segmentation allows the reference voltage regulation to respond more quickly to high-frequency spikes, as the distributed capacitance presents a lower impedance at high frequencies while maintaining adequate noise attenuation.
Solution Approach 2:
The solution transitions from a single-dimensional approach (one large capacitor) to a multi-dimensional approach by adding frequency selectivity through parallel RC networks. Each RC network is tuned to different frequency ranges, providing effective noise attenuation across the entire high-frequency spectrum without the response time penalty of a single large capacitor.
4Speed
If low buffer output impedance is used to improve response time with large capacitive load, then response time is improved, but power consumption increases significantly
Solution Approach 1:
The buffer is divided into multiple parallel output stages, each driving a portion of the total capacitive load. This segmentation allows each buffer stage to operate at higher impedance with lower power consumption, while the combined parallel output maintains the low effective impedance needed for fast response time.
Solution Approach 2:
The buffer employs periodic switching between different output impedance states, using high-impedance high-efficiency paths during steady-state operation and switching to low-impedance fast-response paths only when rapid voltage changes are detected, thereby achieving fast response without continuous high power consumption.
Data Source
AI summary
A time-to-digital converter (TDC) that combines the energy efficiency of a successive approximation (SAR) design with the high speed of pipelined converters by leveraging the inherently pipelined nature of time-domain signaling. The TDC achieves high speed by removing a comparator decision from a signal path, instead using AND/OR gates to separate early and late edges. The TDC uses a pipelined SAR architecture to digitize a differential delay between two incoming clock edges with high speed and low power consumption. Described is a modular digital reference voltage generator that can be used for a capacitive digital-to-analog converter (DAC). The generator comprises a decoupling capacitor, one or more clocked comparators, and power transistor(s). A simplified digital low dropout (LDO) circuitry is used to provide fast reference voltage generation with minimal overhead. The LDO circuitry is arrayed using time-interleaved synchronous clocks or staggered asynchronous clocks to provide finer timing resolution.