Pipelined SAR TDC Delay Architecture for Concurrent Signal Conversion
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Solution Overview
Problem
Existing electronic device architectures face challenges in achieving high speed, throughput, and miniaturization, particularly in computing applications that require concurrent signal processing.
Innovation Solution
The implementation of a pipelined-successive approximation register (SAR) time-to-digital converter (TDC) architecture with a delay architecture, which includes a common-mode voltage-time-converter and a delay difference generation device, enables concurrent processing of multiple input time-domain samples.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional ADC architecture is used, then the device can process signals, but the device complexity and size increase, and throughput is limited
Solution Approach 1:
The ADC is divided into multiple independent stages (first stage with flash TDC and second stage with SAR TDC), each handling specific portions of the conversion process. This segmentation allows parallel processing of different signal components, increasing throughput while keeping each stage's complexity manageable.
Solution Approach 2:
The patent transitions from traditional voltage-domain conversion to time-domain conversion by transforming the analog input signal into time intervals that are then digitized. This dimensional change enables concurrent processing of multiple samples through time-interleaved architectures, improving throughput without proportionally increasing complexity.
2Speed
If higher speed processing is implemented, then throughput improves, but device size and power consumption increase
Solution Approach 1:
The patent employs time-interleaved sampling where multiple conversion stages operate in periodic cycles, each handling specific time slots. This periodic operation allows high-speed processing to be achieved through temporal multiplexing rather than requiring all processing resources to be simultaneously active, reducing overall device area.
Solution Approach 2:
The patent uses simplified copy structures in the time-domain conversion stages, where repetitive modular units process different time intervals of the same signal. This copying approach achieves high throughput through temporal replication rather than spatial replication, minimizing device area while maintaining processing speed.
3Productivity
If multiple concurrent signals are processed, then throughput increases, but device complexity increases
Solution Approach 1:
The conversion process is segmented into distinct functional blocks (flash TDC for coarse conversion, SAR TDC for fine conversion) that can operate independently on different signal streams. This segmentation enables concurrent processing of multiple signals through parallel stage operation while keeping each block's internal complexity low.
Solution Approach 2:
The first stage performs preliminary time-domain conversion of the analog signal into a coarse digital representation, which is then refined by the second stage. This preliminary action allows subsequent stages to process simplified data, enabling concurrent processing of multiple signals without requiring all stages to handle full-complexity conversions simultaneously.
Data Source
AI summary
Aspects of this technical solution can include a plurality of SAR TC stages configured to convert an input time signal to a digital code including a plurality of output signals each corresponding to a SAR TDC stage among the plurality of SAR TDC stages connected to an input of a following SAR TDC stage among the plurality of SAR TDC stages, where the SAR stage is controlled by a clock signal based on a delayed clock signal from a previous SAR TDC stage among the plurality of SAR TDC stages.