Pipelined Storage Circuits for Single-Cycle Read-Modify-Write
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Solution Overview
Problem
Current integrated circuits with storage blocks in programmable logic devices face inefficiencies in executing read-modify-write operations, particularly due to the need for multiple clock cycles and limitations in handling wide data paths, which are exacerbated by the mismatch between data path width and storage interface width.
Innovation Solution
Implementing pipelined circuitry with cascaded processing and storage circuits that partition wide data paths into subsets, allowing each processing and storage circuit to operate on a subset, thereby completing read-modify-write operations within a single clock cycle using pipeline registers and dual-port memory arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional storage blocks are used for read-modify-write operations, then the circuit area is reduced, but the operation latency increases to multiple clock cycles
Solution Approach 1:
The patent divides the wide data path into multiple subsets, with each processing circuit handling a specific subset. This segmentation allows parallel processing of different data portions simultaneously, reducing the overall operation latency from multiple clock cycles to a single clock cycle while maintaining circuit efficiency
Solution Approach 2:
The patent introduces a new dimensional approach by organizing processing circuits and storage circuits in a pipelined architecture where data flows through multiple stages. This dimensional reorganization transforms the traditional sequential read-modify-write operation into a parallel pipeline process, achieving single-clock-cycle completion
2Productivity
If caching circuitry is added to track recent operations, then the operation efficiency is improved, but the circuit area increases
Solution Approach 1:
The patent designs processing circuits that can handle multiple operations including read-modify-write, additions, and multiplications within a unified pipelined architecture. This multi-functionality eliminates the need for separate caching circuitry to track different operation types, maintaining high productivity without increasing circuit area
Solution Approach 2:
The pipelined processing circuits are designed to automatically manage their own operation pipelines, with each stage independently processing data subsets. This self-service capability removes the need for external caching circuitry to coordinate and track operations across multiple clock cycles
3Productivity
If the data path width is increased for higher bandwidth, then the processing capability is improved, but the mismatch with storage interface width causes inefficiency
Solution Approach 1:
The patent segments the wide data path into multiple narrower subsets that match the storage interface width. Each processing circuit handles one subset, and the results are combined at the output. This segmentation eliminates interface mismatch complexity while preserving the high bandwidth capability of the wide data path
Solution Approach 2:
The patent introduces pipeline registers as intermediary elements between processing circuits and storage circuits. These registers buffer and synchronize data flow, mediating the width mismatch between the wide data path and the narrower storage interface, thereby enabling efficient high-bandwidth operations without complexity
Data Source
AI summary
An integrated circuit may have processing and storage circuits that perform read-modify-write operations on a wide data path. A CAD tool may partition the wide data path into data path subsets based on the width of the wide data path, the characteristics of the processing and storage circuits, and various constraints such as resource constraints and timing constraints. The CAD tool may also instantiate corresponding pipelined circuitry. The pipelined circuitry may be arranged in slices with cascaded processing and storage circuits. Each processing and storage circuit in a slice may perform a read-modify-write operation based on the corresponding data path subset and any prior result produced by other processing and storage circuits.