Pipelined Translation Engine for Virtual Memory Address Processing
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Solution Overview
Problem
Current address translation engines in computer systems can only process one request at a time, leading to low translation throughput and high queuing latencies, especially when handling multiple threads and virtualization levels.
Innovation Solution
A pipelined translation engine is introduced, allowing multiple translation requests to be processed simultaneously through different stages of the pipeline, with a first pipeline stage receiving an original address or address translation table entry, a second stage using this value for translation operations, and a third stage issuing read requests for the next address translation table, closely integrated with a table cache pipeline to reduce latency and increase throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a traditional address translation engine processes one request at a time, then the translation accuracy is maintained, but the translation throughput is low and queuing latency is high
Solution Approach 1:
The address translation engine is divided into multiple pipeline stages, where each stage processes a different aspect of the translation request simultaneously. This segmentation allows multiple requests to be in different stages of processing at the same time, increasing throughput while maintaining accuracy through staged validation.
Solution Approach 2:
The pipeline stages perform preliminary actions in sequence, with each stage preparing and validating data before passing it to the next stage. This preliminary processing at each stage ensures that when a request reaches the final stage, all necessary translations and validations are already complete, reducing overall latency.
2Productivity
If multiple translation requests are processed simultaneously through pipeline stages, then translation throughput increases, but the device complexity increases
Solution Approach 1:
By segmenting the translation engine into discrete pipeline stages, each stage can be independently designed and optimized. This modular approach manages complexity by breaking down the monolithic translation function into smaller, more manageable units that can be processed in parallel.
Solution Approach 2:
The pipeline structure allows dynamic processing where requests flow through different stages at different times. This dynamic approach enables the system to handle variable workloads efficiently while maintaining a relatively simple static hardware structure, as the complexity is managed through time-multiplexed processing.
Data Source
AI summary
A translation engine for a processor system to translate virtual memory addresses to physical addresses of a main memory of a computer system is provided, where a sequence of accesses to multiple address translation tables is performed to support a computer system virtualization level. The translation engine includes: a first pipeline having at least, a first pipeline stage to receive a value for an original address or an address translation table entry requested in a previous pass through the first pipeline; a second pipeline stage using the value as an operand in a translation operation eventually yielding the address translation result or yielding a table index to an entry in a next address translation table; and a third pipeline stage issuing a read request for the entry in the next address translation table.