Pipelined Trellis State Updates for High-Speed Decoding

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Solution Overview

Problem

Current trellis-based decoding techniques are constrained by their recursive nature, leading to inefficiencies in state-update calculations and increased hardware requirements, particularly in parallel processing scenarios where data dependency and memory access issues become significant.

Innovation Solution

Implementing a pipelined process that calculates state metrics at non-adjacent time indices independently, using a round-robin scheduling algorithm and combining with windowing and tiling techniques to reduce data dependency and enhance processing speed, allowing a single state-update unit to replace multiple units, thereby reducing circuit area and memory access constraints.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple state-update units are used in parallel to speed up processing, then processing speed is improved, but device complexity and circuit area increase linearly

Engineering Contradiction:
Improveprocessing speedVSAvoidcircuit area
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The trellis is divided into multiple independent sections (tiles or windows) that can be processed separately. Each section contains a subset of time indices and states that can be decoded independently of other sections, allowing the use of a single state-update unit to process different sections sequentially while maintaining high throughput.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Forward state metrics are calculated for all sections before backward state metrics are calculated. This preliminary calculation allows the backward pass to proceed independently using previously computed forward metrics, enabling efficient pipelined processing without requiring multiple simultaneous state-update units.

Inventive Principle:
Principle #10Preliminary action

2Device complexity

If the entire trellis is processed in series by the same processor, then device complexity is reduced, but processing speed decreases

Engineering Contradiction:
Improvenumber of processorsVSAvoidprocessing speed
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The trellis is segmented into independent sections that can be processed in parallel by a single state-update unit using pipelined techniques. The state-update unit processes different sections at different pipeline stages, achieving high throughput without requiring multiple identical processors.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The single state-update unit processes different trellis sections in a periodic manner, cycling through sections in a predetermined sequence. This periodic processing pattern allows the unit to maintain high utilization while processing the entire trellis efficiently.

Inventive Principle:
Principle #19Periodic action

3Productivity

If trellis is broken into sections for parallel processing, then processing speed is improved, but memory access constraints and collision risks increase

Engineering Contradiction:
Improveprocessing speedVSAvoidmemory access constraints
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The trellis is divided into sections with carefully designed boundaries that minimize overlapping memory access patterns. Each section is assigned a specific range of time indices and states, allowing the memory interface to be simplified and collision risks to be reduced through systematic memory management.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Forward state metrics are pre-calculated and stored in memory before the backward pass begins. This preliminary action allows the backward state-update to read from memory without interfering with ongoing forward pass calculations, eliminating memory access conflicts and simplifying the memory interface requirements.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7698624B2Scheduling pipelined state update for high-speed trellis processing
Publication Date: 2010.04.13 TRELLISWARE TECHNOLOGIES INC
  • US7698624B2 patent drawing
  • US7698624B2 patent drawing
  • US7698624B2 patent drawing

AI summary

Methods, apparatuses, and systems are presented for extracting information from a received signal resulting from a process capable of being represented as a finite state machine having a plurality of states, wherein transitions between the states can be represented by a trellis spanning a plurality of time indices, involving calculating branch metrics taking into account the received signal, calculating state metrics at each time index by taking into account the branch metrics and using a pipelined process, wherein the pipelined process is used to calculate state metrics at a first time index, wherein the pipelined process is then used to calculate state metrics at one or more non-adjacent time indices, and wherein the pipelined process is then used to calculate state metrics at an adjacent time index, and generating at least one output taking into account state metrics for states associated with at least one selected path through the trellis.