Pipelined Vector Signaling FEC for Low-Latency Error Correction
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Solution Overview
Problem
High-speed communications systems face challenges in minimizing error correction latency and power consumption while maintaining low Bit Error Rates (BER) in chip-to-chip communication links with low uncorrected BER, especially with existing Forward Error Correction (FEC) techniques that introduce significant latency and computational power consumption.
Innovation Solution
The implementation of pipelined Forward Error Correction (FEC) using vector signaling codes, where error correction syndrome values are incrementally updated as data bits are received, allowing for efficient error detection and correction with reduced latency by utilizing a check matrix and bit error masks within multiple processing phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional Forward Error Correction (FEC) techniques are used, then error correction capability is improved, but latency increases
Solution Approach 1:
The patent divides the FEC processing into multiple parallel pipelines, where each pipeline processes a portion of the data stream simultaneously. This segmentation allows error correction to be performed on smaller chunks of data in parallel, reducing the overall latency while maintaining the required error correction capability for high-speed serial interfaces.
Solution Approach 2:
The patent performs preliminary error correction processing by calculating syndrome values incrementally as data bits are received, rather than waiting for complete data blocks. This preliminary action enables earlier detection and correction of errors, reducing the latency associated with traditional FEC methods that require complete data reception before processing.
2Reliability
If conventional Forward Error Correction (FEC) techniques are used, then error correction capability is improved, but power consumption increases
Solution Approach 1:
The patent segments the FEC processing into multiple specialized pipelines, each handling specific aspects of error correction. This segmentation allows for more efficient resource utilization and reduces the overall computational power required compared to a single monolithic FEC processor, as each pipeline can be optimized for its specific function and operate independently.
Solution Approach 2:
The patent changes the processing parameters by using incremental syndrome value updates instead of reprocessing entire data blocks. This parameter change from batch processing to incremental processing significantly reduces the computational complexity and power consumption while maintaining the same error correction capability.
3Loss of time
If pipelined FEC is implemented, then latency is reduced, but device complexity increases
Solution Approach 1:
The patent divides the complex FEC processing into multiple simpler parallel pipelines, where each pipeline handles a specific stage or portion of the error correction process. This segmentation transforms a single complex sequential process into multiple simpler parallel processes, reducing latency while the modular structure helps manage the overall device complexity through organized functional blocks.
Solution Approach 2:
The patent merges multiple processing functions into integrated pipeline stages that perform multiple operations in sequence. By combining related functions into unified processing blocks within the pipeline, the patent reduces the overall device complexity compared to having separate independent circuits for each function, while still achieving the latency benefits of pipelined processing.
Data Source
AI summary
Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.