Pitch Division Patterning for BEOL Interconnect Overlay Margin
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving precise overlay control and scaling of via pitches and critical dimensions in integrated circuits, as current lithographic technologies struggle to maintain accuracy and resolution, especially at nanometer scales, leading to issues with line width roughness, critical dimension uniformity, and increased costs due to the need for multiple masks.
Innovation Solution
The proposed solution involves a pitch division patterning approach that doubles the overlay margin for via and plug patterning by using a process flow that includes sacrificial hardmask layers, atomic layer deposition, and isotropic spacer etches, allowing for independent patterning of metal lines and vias, which relaxes constraints on lithography equipment and reduces the number of alignment and exposure steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used for via patterning, then the process is simple and direct, but the overlay precision deteriorates as via pitch scales down to 70nm or less
Solution Approach 1:
The patent divides the via patterning process into multiple stages: first forming mandrels at a relaxed pitch, then using spacer deposition and removal cycles to subdivided the pitch into finer features. This segmentation allows the final via pitch to be much smaller than the initial lithographic feature size, achieving sub-70nm precision without requiring proportional lithographic resolution.
Solution Approach 2:
The patent performs preliminary patterning of mandrels at a larger, more manageable pitch before the final via formation. The mandrels serve as templates that guide subsequent spacer deposition, allowing the critical via dimensions to be defined by the spacer thickness rather than direct lithography, thereby achieving higher precision in the final step.
2Length of moving object
If via critical dimension is reduced to maintain scaling, then device density increases, but line width roughness and critical dimension uniformity deteriorate
Solution Approach 1:
The patent introduces spacers as an intermediary element that mediates between the lithographically-defined mandrels and the final via features. The spacer thickness, controlled by atomic layer deposition, defines the via critical dimension with high uniformity, decoupling the via CD control from the limitations of direct lithographic resolution and reducing line width roughness.
3Length of moving object
If multiple lithographic masks are used to achieve smaller pitches, then via pitch resolution improves, but device complexity and processing time increase
Solution Approach 1:
The patent employs self-aligned spacer formation where the spacers automatically position themselves relative to the mandrels through conformal deposition. This self-alignment mechanism eliminates the need for multiple lithographic alignment steps, as the spacer geometry is determined by the mandrel position and deposition thickness rather than additional mask patterns, thereby reducing device complexity while achieving fine pitch.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables continued scaling of metal layer pitches beyond the resolution limits of current lithography, achieves Angstrom-level precision in spacing, and reduces processing time and costs by doubling the edge placement error budget and maximizing the overlay process window.
Implementation Method 1
forming a first conformal dielectric material layer over the first plurality of conductive lines using atomic layer deposition
Implementation Method 2
performing an isotropic spacer etch that laterally erodes the sacrificial material
Data Source
AI summary
Pitch division patterning approaches with increased overlay margin for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a method includes forming a first plurality of conductive lines in a first sacrificial material formed above a substrate. The first plurality of conductive lines is formed along a direction of a BEOL metallization layer and is spaced apart by a pitch. The method also includes removing the first sacrificial material, forming a second sacrificial material adjacent to sidewalls of the first plurality of conductive lines, and then forming a second plurality of conductive lines adjacent the second sacrificial material. The second plurality of conductive lines is formed along the direction of the BEOL metallization layer, is spaced apart by the pitch, and is alternating with the first plurality of conductive lines. The method also includes removing the second sacrificial layer.