Pitch Multiplication for Sub-Resolution IC Feature Patterning
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Solution Overview
Problem
The continuous reduction in feature size of integrated circuits poses challenges for masking techniques, as photolithography has a minimum pitch limit beyond which features cannot be formed reliably, limiting the reduction in size of integrated circuit components.
Innovation Solution
The implementation of pitch multiplication techniques, which involve forming spacers on a substrate to effectively halve the pitch, allowing for the formation of smaller features by using a combination of photolithography and etching processes, and the use of multiple masks to create features of different sizes in array and peripheral regions of integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If photolithography is used to define features, then manufacturing process is simplified, but minimum pitch limit prevents further feature size reduction
Solution Approach 1:
The patent divides the feature definition process into multiple stages: first forming mandrels at a relaxed pitch, then using pitch multiplication to create spacers that define the final fine-pitch features. This segmentation allows the photolithography step to operate at its minimum pitch limit while achieving smaller final feature sizes through the spacer formation process.
Solution Approach 2:
The patent performs preliminary actions by first forming mandrels and spacers before defining the final feature pattern. The spacers are formed in advance as sacrificial structures that guide the subsequent etching process, enabling precise feature definition at pitches below the photolithography minimum.
2Adaptability or versatility
If multiple masks are used to create features of different sizes, then pattern flexibility is improved, but device complexity increases
Solution Approach 1:
The patent makes the spacer structure multi-functional: it serves as both a pattern definition template for fine-pitch features and a sacrificial mask that is selectively removed to expose specific regions. This universality allows a single spacer structure to enable both array region patterning and peripheral region access without requiring separate masks for each function.
Solution Approach 2:
Instead of using multiple masks to directly define all features, the patent inverts the approach by forming a continuous spacer structure and then selectively removing portions to create the desired pattern. The features are defined by what is removed rather than what remains, simplifying the masking process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of smaller features and conductive lines in integrated circuits, increasing storage capacity and improving the flexibility in defining circuit patterns, while reducing the number of masks required from three to two, thus simplifying the fabrication process.
Implementation Method 1
defining a plurality of features in a first photoresist layer using photolithography
Implementation Method 2
A pattern of trenches is etched in the substrate through the features in the lower masking layer
Data Source
AI summary
A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.