Pitch Multiplication for Memory Word Line Feature Size Reduction
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Solution Overview
Problem
Photolithographic techniques face a limit in reducing feature sizes due to their minimum pitch, hindering the creation of smaller and denser integrated circuitry, particularly in memory devices like flash memory where feature size reduction is essential for increased density.
Innovation Solution
The method involves pitch multiplication by depositing spacer-forming layers that are anisotropically etched to form sub-lithographic features, allowing for the formation of narrower conductive lines by halving or further reducing the pitch, enabling the creation of smaller feature sizes beyond the conventional photolithographic resolution limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithographic techniques are used to pattern features, then manufacturing process is well-established and reliable, but minimum pitch limits further feature size reduction
Solution Approach 1:
The pitch multiplication process segments the feature formation into multiple distinct steps: forming mandrels at a first pitch using photolithography, depositing spacer material, selectively removing portions, and repeating the process. This segmentation allows each step to be optimized independently, achieving sub-lithographic pitch while maintaining process reliability.
Solution Approach 2:
The method performs preliminary actions by first forming mandrels at a larger pitch that is within photolithographic capabilities, then using these mandrels as templates for subsequent spacer deposition. This preliminary structuring enables the final sub-lithographic pitch to be achieved through controlled material removal rather than direct patterning.
2Manufacturing precision
If pitch multiplication is used to reduce feature sizes below minimum pitch, then feature size reduction is achieved, but process complexity increases
Solution Approach 1:
The pitch multiplication method embeds multiple patterning cycles within a unified process framework. Each cycle nests spacer deposition, selective removal, and mandrel formation steps, with the output of one cycle becoming the input for the next. This nesting achieves complex pitch reduction while organizing process steps in a systematic, repeatable manner.
Solution Approach 2:
Spacer material serves as an intermediary element between the photolithographically-formed mandrels and the final sub-lithographic features. The spacer material is deposited conformally, then selectively removed to create the desired pitch multiplication, acting as a mediator that enables transition from lithographic to sub-lithographic dimensions.
3Ease of manufacture
If conventional photolithography is used, then process is simpler and more direct, but feature width cannot be reduced below minimum pitch
Solution Approach 1:
The method replaces direct photolithographic patterning (optical/mechanical system) with a chemistry-based spacer deposition and selective removal process. This substitution uses conformal film deposition and anisotropic etching to achieve pitch multiplication, bypassing the optical resolution limits of photolithography while maintaining manufacturing simplicity through standardized semiconductor process steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of narrower conductive lines, such as word lines, with reduced pitch, facilitating the creation of smaller and denser integrated circuitry, specifically in memory arrays, thereby overcoming the limitations of traditional photolithography in feature size reduction.
Implementation Method 1
The spacer-forming layer is anisotropically etched to form sub-lithographic features
Data Source
AI summary
Methods of forming features such as word lines of memory circuitry are disclosed. One such method includes forming an initial pitch multiplied feature pattern extending from a target area into only one of a first or second periphery area received on opposing sides of the target area. Thereafter, a subsequent feature pattern is formed which extends from the target array area into the other of the first or second periphery area. The initial and subsequent feature patterns may be used in forming features in an underlying material which extend from the target area to the first and second periphery areas. Other embodiments are disclosed.