Pitch-Multiplication for Sub-Lithographic Semiconductor Features
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Solution Overview
Problem
Current lithographic processes face limitations in forming and utilizing sub-lithographic features, which restrict the density of integrated circuit patterns and hinder the miniaturization of electronic components.
Innovation Solution
The method involves pitch-multiplication techniques, where a material with sub-lithographic thickness is deposited and anisotropically etched to form features with distinct sidewalls, allowing for selective filling of gaps by masking material, enabling the creation of higher density circuit patterns beyond conventional lithographic capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used, then manufacturing simplicity is maintained, but pitch multiplication capability deteriorates (cannot form sub-lithographic features)
Solution Approach 1:
The patent segments the formation of sub-lithographic features into distinct stages: first forming mandrels at a relaxed pitch, then depositing and anisotropically etching material to create the final sub-lithographic features. This segmentation allows each stage to be optimized independently, achieving pitch multiplication while maintaining manufacturing feasibility
Solution Approach 2:
The patent performs preliminary actions by first forming mandrels and depositing sacrificial material before the final anisotropic etching step. This preliminary structuring enables precise control over the final feature dimensions and spacing, achieving sub-lithographic pitch multiplication with controlled precision
2Manufacturing precision
If pitch multiplication is implemented to extend lithographic capabilities, then pitch capability is improved, but processing difficulties increase
Solution Approach 1:
The patent changes material parameters by selecting specific sacrificial materials with appropriate etch selectivity and deposition characteristics. By adjusting material properties rather than process parameters, the patent achieves pitch multiplication while simplifying the processing steps required
Solution Approach 2:
The patent introduces intermediary structures (mandrels and sacrificial material layers) that mediate between the lithographic process and the final sub-lithographic features. These intermediaries enable pitch multiplication by providing a template that guides the formation of final features, reducing direct processing complexity
3Manufacturing precision
If sub-lithographic features are formed by depositing material with thickness less than minimum lithographic feature size, then feature size precision is improved, but anisotropic etching difficulties increase
Solution Approach 1:
The patent applies local quality by creating regions of different material composition and structure within the deposited layer. The sacrificial material is positioned specifically where needed to define feature locations, allowing anisotropic etching to proceed with high precision while managing complexity through localized material properties
Solution Approach 2:
The patent exploits asymmetry in the anisotropic etching process by designing mandrel and sacrificial material geometries that create asymmetric etch profiles. This asymmetry enables precise control over feature dimensions and spacing, achieving sub-lithographic precision while the etching process itself remains relatively simple
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of sub-lithographic features with reduced pitch, enhancing the density of integrated circuit patterns and enabling smaller electronic components, thereby extending the capabilities of lithographic techniques.
Implementation Method 1
depositing a material to have a thickness which is less than that of the minimum capable lithographic feature size
Implementation Method 2
The material may be anisotropically etched to form the sub-lithographic features
Data Source
AI summary
Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a method of forming a semiconductor construction. Features are formed over a base. Each feature has a first type sidewall and a second type sidewall. The features are spaced from one another by gaps. Some of the gaps are first type gaps between first type sidewalls, and others of the gaps are second type gaps between second type sidewalls. Masking material is formed to selectively fill the first type gaps relative to the second type gaps. Excess masking material is removed to leave a patterned mask. A pattern is transferred from the patterned mask into the base.


