Pitch-Multiplied Semiconductor Loop Isolation
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Solution Overview
Problem
The continued reduction in feature sizes of integrated circuits poses challenges for photolithographic techniques, as they reach their minimum pitch and critical dimension limits, necessitating innovative methods for forming small features and maintaining process efficiency.
Innovation Solution
The implementation of pitch multiplication methods, where spacers are formed on mandrels to create closely spaced lines, and isolation transistors are used to electrically isolate loop legs without the need for a loop etch, simplifying the process flow and allowing for feature sizes below the minimum photolithographic pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithographic techniques are used to form features, then manufacturing process is simple, but minimum pitch and critical dimension limits prevent further feature size reduction
Solution Approach 1:
The pitch multiplication process segments the feature formation into multiple stages: first forming mandrels at a relaxed pitch, then using spacer deposition and mandrel removal to create final features at half the original pitch. This segmentation allows bypassing photolithographic resolution limits while maintaining process control.
Solution Approach 2:
Mandrels are formed in advance at a larger pitch that is within photolithographic capabilities, and then used as templates for subsequent spacer formation. This preliminary action enables the final small features to be created through a controlled multi-step process rather than direct photolithography.
2Reliability
If loop etch is performed to electrically isolate loop legs, then electrical isolation is achieved, but process steps increase and throughput decreases
Solution Approach 1:
The loop etch step is completely removed from the process flow. Electrical isolation of loop legs is achieved through alternative means (such as using the spacer structure itself or adjacent isolation structures) rather than etching the loop, thereby eliminating a process step while maintaining the required electrical isolation.
Solution Approach 2:
The functions of loop formation and electrical isolation are merged into a single integrated structure. The spacers that define the pitch-multiplied features also serve as the isolation structures, eliminating the need for separate loop etch processing.
3Manufacturing precision
If pitch multiplication is implemented to achieve smaller pitches, then feature density increases, but process steps increase
Solution Approach 1:
The spacer material self-aligns to the mandrels through conformal deposition, automatically defining the position and pitch of the final features. This self-service mechanism eliminates the need for additional alignment steps and photolithography processes that would otherwise be required to achieve the same pitch reduction.
Solution Approach 2:
The pitch is controlled by changing the deposition thickness parameter of the spacer material rather than by photolithographic patterning parameters. This parameter change approach allows precise pitch control through a single critical dimension (spacer thickness) that can be controlled by atomic layer deposition or chemical vapor deposition processes.
Data Source
AI summary
Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.