Variable Fin Structures With Selective Width Trimming by Pitch
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Solution Overview
Problem
Fin field effect transistors (finFETs) experience performance degradation due to fin size variations across different areas of an integrated circuit (IC), leading to compromised gate control and transistor mismatches, which existing fabrication processes attempt to address but often result in bending or collapsing of narrow fins, reducing IC yield.
Innovation Solution
A method for variable fin width trimming, where fins in sparse pitch areas undergo greater width reduction than those in tight pitch areas, using techniques like etching, to maintain structural integrity and enhance short channel control, allowing for selective width adjustment of silicon and silicon-germanium fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If existing fabrication processes are used to address fin size variations, then fin width control is improved, but fin structural integrity deteriorates (bending or collapsing of narrow fins)
Solution Approach 1:
The patent applies local quality by implementing region-specific etching processes that target only sparse pitch areas for fin width reduction. Tight pitch areas are excluded from the etching process, preserving their original fin dimensions and structural integrity. This localized approach allows different fin regions to have optimized dimensions suitable for their specific pitch conditions without compromising overall device reliability.
2Adaptability or versatility
If fin size variation is allowed across different IC areas, then device adaptability is improved, but IC performance deteriorates due to gate control loss and transistor mismatches
Solution Approach 1:
The patent implements local quality by creating distinct fin structures optimized for different pitch regions. Sparse pitch areas receive etching treatment to reduce fin width and improve gate control, while tight pitch areas maintain larger fin dimensions for structural stability. This localized differentiation resolves the contradiction by allowing each region to have adaptability suited to its specific pitch conditions while maintaining overall IC performance through controlled uniformity within each region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates fin width variations, enhancing short channel control and transistor performance by selectively reducing fin widths in sparse pitch areas while preserving the integrity of those in tight pitch areas, thereby improving IC yield and reliability.
Implementation Method 1
A method for variable fin width trimming, where fins in sparse pitch areas undergo greater width reduction than those in tight pitch areas, using techniques like etching
Data Source
AI summary
The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.