CMOS Image Sensor AD Conversion Using Variable Reference Slope
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Solution Overview
Problem
Digital cameras using CMOS image sensors face challenges in achieving high-speed readout and high resolution due to variations in manufacturing elements of comparators, leading to errors in analog-to-digital (AD)-converted data, and difficulties in increasing circuit area and power consumption.
Innovation Solution
An imaging apparatus comprising a pixel for generating a signal through photoelectric conversion, a comparing circuit for comparing the signal with a time-dependent reference signal, a counter circuit for counting until the magnitude relation inversion, and a selecting circuit for setting the time-dependent change rate of the reference signal based on the signal level, allowing for efficient AD conversion with reduced bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple comparators are used for AD conversion, then high-speed readout and high resolution can be achieved, but manufacturing variations cause response speed differences leading to AD conversion errors
Solution Approach 1:
The patent merges multiple comparator functions into a single comparator by sequentially comparing the input signal with multiple different reference signals (first reference signal for high-order bits, second reference signal for low-order bits). This eliminates manufacturing variations between multiple comparators while achieving multi-bit AD conversion, resolving the contradiction between precision and reliability.
Solution Approach 2:
The patent segments the AD conversion process into two stages: first comparing the signal with a first reference signal to obtain high-order bits, then comparing with a second reference signal to obtain low-order bits. This segmentation allows a single comparator to achieve multi-bit conversion accuracy without suffering from manufacturing variations affecting multiple comparators simultaneously.
2Measurement precision
If multiple comparators are used for AD conversion, then high resolution can be achieved, but circuit area increases
Solution Approach 1:
The patent combines the functionality of multiple comparators into a single comparator that sequentially performs multiple comparison operations using different reference signals. This merging approach achieves multi-bit AD conversion resolution while using only one comparator circuit, dramatically reducing the circuit area compared to using multiple parallel comparators.
Solution Approach 2:
The patent uses periodic switching between different reference signals (first reference signal and second reference signal) to enable a single comparator to perform multiple comparison functions sequentially. This periodic action allows one comparator to replace multiple comparators, reducing circuit area while maintaining conversion resolution.
3Measurement precision
If multiple comparators are used for AD conversion, then high resolution can be achieved, but power consumption increases
Solution Approach 1:
The patent merges multiple comparator operations into a single comparator that sequentially compares the input signal with different reference signals. This reduces power consumption by eliminating the need for multiple simultaneously operating comparators, while still achieving multi-bit AD conversion resolution through sequential comparison stages.
Solution Approach 2:
The patent employs periodic switching between different reference signals to enable a single comparator to perform multiple comparison functions. This periodic operation reduces power consumption compared to having multiple comparators operating simultaneously, while maintaining the resolution benefits of multi-bit conversion.
4Productivity
If the number of bits is reduced for high-speed readout, then readout speed increases, but signal-to-noise ratio may be insufficient
Solution Approach 1:
The patent segments the bit resolution into two sequential comparison stages: first obtaining high-order bits through comparison with a first reference signal, then obtaining low-order bits through comparison with a second reference signal. This segmentation enables sufficient signal-to-noise ratio by capturing both high and low order signal information, while maintaining high readout speed through the sequential process.
Solution Approach 2:
The patent dynamically switches between different reference signals based on the conversion stage. The first reference signal is used for high-order bit extraction, then the second reference signal is used for low-order bit extraction. This dynamic approach optimizes the signal-to-noise ratio at each stage while maintaining overall high-speed readout capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-speed readout and high-resolution AD conversion by reducing the number of bits required, minimizing errors, and optimizing circuit area and power consumption, while maintaining sufficient signal-to-noise ratio.
Implementation Method 1
a pixel for generating a signal by photoelectric conversion
Data Source
AI summary
An imaging apparatus and a method of driving the same that can generate a digital data of a high resolution pixel signal are provided. The imaging apparatus includes: a pixel (10-1) for generating a signal by photoelectric conversion; a comparing circuit (30-1) for comparing a signal based on the pixel with a time-dependent reference signal; a counter circuit (40-1) performing a counting operating until an inversion of a magnitude relation between the signal based on the pixel and the time-dependent reference signal; and a selecting circuit (30-2) for setting a time-dependent change rate of the reference signal, according to a signal level of the signal based on the pixel.