Pixel-Level ADC Readout for High-SNR Digital Focal Plane Arrays
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Solution Overview
Problem
Conventional focal plane arrays (FPAs) face limitations in achieving high frame rates, wide dynamic range, and low power consumption while maintaining signal-to-noise ratio (SNR) due to capacitor size limitations and electronics noise, making them unsuitable for demanding imaging applications like long-wave infrared imaging.
Innovation Solution
A two-dimensional array of self-contained analog-to-digital converters (ADCs) that convert current mode signals to digital signals within each pixel, eliminating the need for large charge storage capacitors and highly linear analog electronics, and enabling digital signal processing, such as filtering and data compression, directly on the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional analog readout designs are used to achieve high frame rates, then pixel saturation is avoided, but capacitor size limitations and readout noise floor prevent scaling
Solution Approach 1:
The patent replaces the analog capacitor-based integration system with a digital counting system. Instead of using large capacitors to integrate and store charge analogously, the invention uses digital counters to accumulate photon detection events. This substitution eliminates capacitor size limitations and associated noise floors, enabling both high frame rates and maintained signal-to-noise ratio simultaneously.
Solution Approach 2:
The invention changes the fundamental parameter of charge storage from analog voltage on capacitors to digital count values. By transitioning from continuous analog signals constrained by capacitor physics to discrete digital counts, the system overcomes the trade-off between frame rate and noise performance that plagues conventional analog designs.
2Area of moving object
If capacitor size is reduced to meet area constraints, then pixel area is reduced, but well depth is limited requiring higher frame rates that increase power consumption
Solution Approach 1:
The patent eliminates the capacitor-based well depth limitation by replacing it with a digital counting mechanism. The digital counter can accumulate detection events without the physical area constraints that limit capacitor size, allowing small pixels to maintain adequate dynamic range without requiring high frame rates for saturation avoidance.
Solution Approach 2:
The invention segments the pixel function into separate components: a small photodetector area for photon detection and a digital counting circuit for accumulation. This segmentation allows the detection area to be minimized while the counting function handles dynamic range requirements, breaking the direct link between pixel area and well depth that exists in capacitor-based designs.
3Reliability
If more data output taps are added to transmit sufficient data, then dynamic range is maintained, but device complexity and system size increase
Solution Approach 1:
The patent merges the functions of multiple parallel analog readout channels into a single digital output per pixel. By performing photon counting and accumulation digitally within each pixel, the system consolidates what would otherwise require multiple analog output taps, reducing device complexity while maintaining full dynamic range capability through the digital count value.
4Measurement precision
If analog electronics are used to maintain high linearity, then conversion accuracy is improved, but power consumption increases
Solution Approach 1:
The patent replaces power-hungry analog electronics with low-power digital counting circuits. The digital counter requires minimal power to increment values and store counts, eliminating the need for high-linearity analog amplifiers, transimpedance converters, and associated precision analog circuitry that consume significant power while providing equivalent or superior measurement precision through direct digital counting.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power dissipation and noise, allows operation with lower power supplies, and enables high-resolution imaging with reduced complexity and size, suitable for applications like long-wave infrared imaging, while maintaining high SNR and frame rates.
Implementation Method 1
a capacitor may be employed to integrate charge from the current mode signal and the capacitor and ADC architecture may be selected to determine the least significant bit of each of the ADCs
Data Source
AI summary
Autonomously operating analog to digital converters are formed into a two dimensional array. The array may incorporate digital signal processing functionality. Such an array is particularly well-suited for operation as a readout integrated circuit and, in combination with a sensor array, forms a digital focal plane array.