Digital Focal Plane Readout Using Pixel-Level ADC Arrays
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Solution Overview
Problem
Conventional focal plane arrays (FPAs) face limitations in achieving high frame rates, wide dynamic range, and low power consumption due to capacitor size limitations and electronics noise, making them unsuitable for demanding imaging applications like long-wave infrared imaging.
Innovation Solution
A two-dimensional array of self-contained analog-to-digital converters (ADCs) that convert current mode signals to digital signals within the array, allowing for digital signal processing and reducing the need for large charge storage capacitors and highly linear analog electronics, enabling operation with lower power supplies and smaller feature sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional analog readout designs are used, then capacitor size can be reduced, but frame rate and dynamic range are limited
Solution Approach 1:
The patent replaces the mechanical/electrical analog integration system with a digital counting system. Instead of using large capacitors to integrate and store analog signals, the invention uses digital counters to accumulate photon detection events. This substitution allows frame rates to be increased without being constrained by capacitor size and charge integration time constants, directly resolving the contradiction between productivity (frame rate) and quantity of substance (capacitor size).
Solution Approach 2:
The invention changes the fundamental parameter of signal representation from analog voltage levels (requiring large capacitors for integration) to digital count values. By digitizing the signal at the pixel level, the system can achieve high frame rates and wide dynamic ranges without being limited by capacitor physical dimensions, as the digital counters can rapidly increment and store values without physical constraints.
2Reliability
If analog electronics are used for signal processing, then dynamic range can be achieved, but noise and power consumption increase
Solution Approach 1:
The patent substitutes analog electronics with digital electronics for signal processing. Digital circuits consume significantly less power than analog circuits while providing equivalent or superior signal-to-noise performance. The digital counters and logic circuits replace power-hungry analog amplifiers and filters, directly reducing power consumption while maintaining or improving reliability and signal quality.
Solution Approach 2:
The invention extracts and eliminates the noisy analog signal processing stage from the detection system. By directly converting photons to digital counts at the pixel level without intermediate analog amplification or filtering, the system removes the primary sources of electronic noise and power consumption, achieving high signal-to-noise ratios with minimal energy expenditure.
3Measurement precision
If analog signal processing is used, then signal quality can be maintained, but device complexity and size increase
Solution Approach 1:
The patent replaces complex analog signal processing electronics with simple digital counting circuits. The analog front-end with its multiple amplification stages, filters, and adjustment circuits is substituted with straightforward digital counters and logic. This substitution maintains signal quality through accurate photon counting while dramatically reducing device complexity and size, as digital circuits can be implemented with far fewer components.
Solution Approach 2:
The invention segments the signal processing function to the individual pixel level, where each pixel independently counts photons and generates a digital output. This eliminates the need for centralized analog processing circuits that would increase overall device complexity. Each pixel operates as an independent digital unit, simplifying the overall system architecture while maintaining signal integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-resolution imaging with reduced power dissipation and noise, allowing for smaller, more efficient digital focal plane arrays that can handle high frame rates and wide dynamic ranges, suitable for demanding imaging applications.
Implementation Method 1
a capacitor may be employed to integrate charge from the current mode signal and the capacitor and ADC architecture may be selected to determine the least significant bit of each of the ADCs
Data Source
AI summary
Autonomously operating analog to digital converters are formed into a two dimensional array. The array may incorporate digital signal processing functionality. Such an array is particularly well-suited for operation as a readout integrated circuit and in combination with a sensor array, forms a digital focal plane array.