Pixel-Level ADC Readout Array for Low-Noise Infrared Imaging
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Solution Overview
Problem
Conventional analog to digital converters (ADCs) in focal plane arrays face limitations in achieving wide-area coverage, high signal-to-noise ratios, and high spatial resolution, particularly in long-wave infrared imaging applications, due to capacitor size limitations and noise issues, leading to high power consumption and complex sensor systems.
Innovation Solution
A two-dimensional array of self-contained ADCs that convert current mode signals to digital signals within the array, integrating charge using a capacitor to determine the least significant bit and employing counters for the most significant bit, allowing for digital signal processing and reducing the need for large charge storage capacitors and highly linear analog electronics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional analog ADC designs are used in focal plane arrays, then wide-area coverage and high spatial resolution can be achieved, but capacitor size limitations and noise issues lead to high power consumption and complex sensor systems
Solution Approach 1:
The patent divides the ADC functionality into multiple independent unit cells distributed across the focal plane array. Each unit cell contains its own ADC that converts analog signals to digital signals locally, eliminating the need for large centralized charge storage capacitors and reducing noise propagation. This segmentation allows each ADC to operate independently with smaller capacitors, thereby reducing power consumption while maintaining measurement precision.
Solution Approach 2:
The patent transitions from conventional analog signal processing to digital signal processing by implementing ADCs within each pixel location. This dimensional change from analog to digital domain enables better noise performance and reduces the need for large capacitors, as digital signals can be processed and transmitted more efficiently through the readout circuitry.
2Device complexity
If conventional analog readout designs are used, then analog signals can be converted to digital signals off-chip, but this leads to large, massive, and complex sensor systems with many data output taps
Solution Approach 1:
The patent merges the ADC functionality directly into each pixel location within the focal plane array chip. By combining the analog-to-digital conversion function with the pixel structure, the system eliminates the need for separate off-chip conversion hardware and reduces the number of data output taps required. This integration reduces overall sensor system complexity while maintaining compact chip area.
3Loss of energy
If self-contained ADCs are implemented in each pixel location, then digital signals can be processed within the array with reduced noise and power dissipation, but the ADC circuitry must fit within limited pixel area
Solution Approach 1:
The patent segments the ADC circuitry into compact unit cells that fit within each pixel location. Each unit cell contains minimal necessary components (capacitor, switch, and digital logic) to perform analog-to-digital conversion. This segmentation enables the ADC functionality to be distributed across the array with each instance occupying minimal area, thereby reducing overall power dissipation while fitting within limited pixel area constraints.
Solution Approach 2:
The patent changes the operating parameters of the ADC by using digital rather than analog signal processing. This parameter change from analog to digital domain allows for reduced capacitor sizes and lower power consumption, as digital circuits can operate at lower voltages and frequencies while maintaining signal integrity. The digital output format also enables more efficient data transmission and processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-resolution imaging with reduced power dissipation and noise, allowing for operation with lower power supplies and smaller feature sizes, resulting in a more compact and efficient digital focal plane array capable of wide-area coverage and high SNR.
Implementation Method 1
a capacitor may be employed to integrate charge from the current mode signal and the capacitor and ADC architecture may be selected to determine the least significant bit of each of the ADCs
Data Source
AI summary
Autonomously operating analog to digital converters are formed into a two dimensional array. The array may incorporate digital signal processing functionality. Such an array is particularly well-suited for operation as a readout integrated circuit and, in combination with a sensor array, forms a digital focal plane array.