Pixel Arrangement Controller for Sequential Block Storage
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Solution Overview
Problem
Current image processing methods disperse pixel data across memory, leading to inefficient calculation times during discrete cosine transform (DCT) processing, as pixels of the same block are not stored in sequential addresses, requiring extraction from non-consecutive memory locations.
Innovation Solution
An image processing apparatus with a pixel arrangement controller and two data unit buffers rearranges pixel addresses to store data in sequential blocks, using a formula to calculate addresses and switch between buffers, allowing for batch processing and direct memory access (DMA) efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pixel data is stored sequentially in memory row by row, then memory storage is simple and continuous, but pixels of the same block are dispersed in non-consecutive memory locations, requiring individual extraction and increasing calculation time
Solution Approach 1:
The patent applies preliminary action by pre-arranging pixel data in memory according to block structure before DCT processing. The pixel arrangement controller reorganizes sequentially stored pixels into block-based contiguous storage, so that when DCT processing occurs, all pixels of each block are already positioned contiguously in memory, eliminating the need for individual pixel extraction during processing.
Solution Approach 2:
The patent applies segmentation by dividing the image data into distinct blocks (e.g., 8×8 pixel blocks) and arranging each block as a contiguous unit in memory. This segmentation approach transforms the memory layout from a flat sequential structure to a hierarchical block-based structure, where each block's pixels are grouped together, enabling efficient batch processing during DCT operations.
2Loss of time
If pixels of the same block are extracted from non-consecutive memory locations, then individual pixel processing can be performed, but a lot of calculation time is wasted due to repeated memory access operations
Solution Approach 1:
The patent applies preliminary action by pre-arranging pixel data in memory according to block structure before DCT processing. The pixel arrangement controller reorganizes sequentially stored pixels into block-based contiguous storage, so that when DCT processing occurs, all pixels of each block are already positioned contiguously in memory, eliminating the need for individual pixel extraction during processing.
Solution Approach 2:
The patent applies merging by combining all pixels of the same block into a single contiguous memory location. Instead of keeping pixels dispersed throughout memory, the system merges each block's pixels together in sequential memory addresses, allowing the DCT processor to access entire blocks efficiently as unified data units rather than scattered individual pixels.
3Productivity
If individual pixel movement is performed K times to group a K×K block, then precise block formation is achieved, but processing efficiency is reduced due to repeated individual operations
Solution Approach 1:
The patent applies preliminary action by pre-arranging pixel data in memory according to block structure before DCT processing. The pixel arrangement controller reorganizes sequentially stored pixels into block-based contiguous storage, so that when DCT processing occurs, all pixels of each block are already positioned contiguously in memory, eliminating the need for individual pixel extraction during processing.
Solution Approach 2:
The patent applies mechanics substitution by replacing the mechanical approach of individually moving pixels K times with an automated pixel arrangement controller that performs bulk data reorganization. Instead of manual or iterative pixel-by-pixel manipulation, the system uses a controller implementing address calculation algorithms to automatically reorganize entire blocks of pixel data in a single pass, substituting complex mechanical operations with streamlined computational control.
Data Source
AI summary
The present image processing apparatus includes a pixel arrangement controller and two data unit buffers coupled with the pixel arrangement controller. This controller can rearrange the addresses of the pixels in the corresponding data unit buffer according to the size of the block. Accordingly, the pixel data of the same block can be arranged in sequential addresses of the data unit buffer. Therefore, the pixel data may be processed as a batch.


