Pixel Array Active Device Layout for Flat Display Panels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional flat panel display pixel structures face challenges in reducing current leakage and increasing storage capacitance while maintaining satisfactory electrical performance, leading to potential image flickering due to parasitic capacitance changes and reduced usable area for storage capacitors.
Innovation Solution
The pixel structure incorporates a dual-gate design with a U-shaped or S-shaped pattern for the connection and branch electrodes, reducing the active device layout area and expanding the common electrode layout to increase storage capacitance, while maintaining a high width-to-length ratio for the channel, thereby enhancing display image quality and reducing current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two thin film transistors are connected in series to reduce current leakage, then current leakage is reduced, but the layout area of the active device increases and the storage capacitance cannot be increased
Solution Approach 1:
The pixel structure is divided into two separate thin film transistors (first TFT and second TFT) connected in series, with each TFT having its own gate electrode, source electrode, and drain electrode. This segmentation allows independent optimization of each transistor's layout to minimize total area while maintaining low current leakage through the series connection configuration.
Solution Approach 2:
The source and drain electrodes are extended in multiple directions (forming first and second extension portions) rather than simple linear connections. This dimensional expansion of electrode paths allows the active device to occupy less layout area by utilizing spatial arrangement in multiple directions, thereby freeing up area for the storage capacitor.
2Area of stationary object
If the layout area of the TFTs is reduced to expand the common electrode area, then storage capacitance is increased, but process shifts cause changes in parasitic capacitance leading to image flicker
Solution Approach 1:
The source and drain electrodes are designed with asymmetric extension portions - the source electrode has a first extension portion extending in a first direction, while the drain electrode has a second extension portion extending in a second direction. This asymmetric design, combined with selective overlapping with the common electrode, creates a layout that is less sensitive to process shifts, stabilizing parasitic capacitance values and preventing image flicker.
Data Source
AI summary
A pixel array including a pixel electrode and an active device is provided. The active device includes a gate, a channel layer, a source, a drain, a connection electrode, a first branch portion and a second branch portion. The gate is electrically connected with a scan line. The channel layer located at a side of the gate is electrically isolated from the gate. The source, the drain and the connection electrode are disposed on a part region of the channel layer. The first branch portion disposed on a part region of the channel layer is connected with an end of the connection electrode. The first branch portion surrounds the source located on the channel layer. The second branch portion disposed on a part region of the channel layer is connected with the other end of the connection electrode. The second branch portion surrounds the drain located on the channel layer.