Pixel Array ADC Using Single-Ramp Difference Conversion
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Solution Overview
Problem
Current analog-to-digital conversion techniques in imaging sensors face limitations in speed and accuracy due to the need for high-speed clocking and distribution of counter signals, which can lead to conversion errors and require additional subtraction circuitry, especially in applications like Time Delay and Integration (TDI) where multiple exposures are integrated.
Innovation Solution
The implementation of an analog-to-digital converter that uses a single-direction counter and a ramp signal with optional inversion, allowing concurrent or sequential comparison of analog signals, and includes a control stage to enable counter circuitry based on signal comparisons, reducing the need for counter direction changing circuitry and enabling faster conversion without high-speed clocking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single ADC is used in the output stage with time-shared basis, then device complexity is reduced, but conversion speed deteriorates
Solution Approach 1:
The patent divides the pixel array into multiple blocks, with each block having its own dedicated ADC. This segmentation allows parallel conversion operations across different blocks, improving overall conversion speed while keeping each individual ADC simple and manageable in complexity.
Solution Approach 2:
The patent introduces a spatial dimension to the conversion process by distributing ADCs across different spatial blocks of the pixel array. Instead of a single time-shared ADC, multiple ADCs operate simultaneously in different spatial locations, transforming a temporal bottleneck into a parallel spatial operation.
2Measurement precision
If counter direction changing circuitry is used, then measurement precision is improved, but device complexity increases
Solution Approach 1:
Instead of changing the counter direction to handle different signal levels, the patent inverts the approach by always counting upward and using subtraction logic. The difference between two upward counts (representing different signal levels) is calculated by subtracting the smaller count from the larger count, eliminating the need for direction-changing circuitry.
Solution Approach 2:
The patent extracts the direction-changing functionality from the counter circuitry and replaces it with a simpler subtraction operation. By separating the magnitude measurement (always positive count) from the difference calculation (subtraction), the complex direction control logic is removed while maintaining measurement precision.
3Productivity
If high-speed clocking is used, then conversion speed is improved, but measurement precision deteriorates due to clock skew
Solution Approach 1:
The patent uses a replica of the signal path through the pixel circuitry to generate a reference signal that experiences the same delays as the main signal. By comparing the main signal against this delayed reference, the patent compensates for clock skew and propagation delays, maintaining precision even at higher conversion speeds.
Solution Approach 2:
The patent measures the actual propagation delay through the signal path and uses this information to adjust the timing or compensation values. This feedback mechanism allows the system to adapt to variations in signal propagation and maintain accurate conversions without requiring excessively high clock speeds.
4Measurement precision
If additional subtraction circuitry is used, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent makes the ADC counter serve multiple functions: it measures both the first signal level and the second signal level, and also performs the subtraction operation to generate the difference. This multi-functionality eliminates the need for separate subtraction circuitry while maintaining precise difference measurement.
Solution Approach 2:
The patent merges the conversion and subtraction operations into a single integrated process. By converting both signals using the same counter mechanism and then subtracting the digital values, the patent combines multiple functions into unified circuitry, reducing overall device complexity while preserving measurement precision.
Data Source
AI summary
An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.