Pixel Array ADC Architecture for Fast Low-Skew Conversion
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Solution Overview
Problem
Existing analog-to-digital conversion techniques in imaging sensors are limited by the need for rapid and accurate conversion of analog signals, which is constrained by the period of the ramp signal and clock frequency, leading to conversion errors due to clock skew and noise variations across columns.
Innovation Solution
A dedicated clock system for each analog-to-digital converter allows for local clock generation and calibration, enabling faster and more accurate conversion by comparing analog signals with a ramp signal, using reference signals for calibration, and potentially operating at high frequencies, thus reducing power consumption and increasing conversion speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single ADC is used in the output stage for time-shared conversion by column circuits, then device complexity is reduced, but conversion speed and productivity deteriorate due to sequential processing
Solution Approach 1:
The patent divides the pixel array into multiple blocks, with each block having its own dedicated ADC. This segmentation allows parallel conversion of multiple columns simultaneously, increasing productivity while keeping individual ADC circuits relatively simple. The block-based architecture enables spatial distribution of conversion tasks.
Solution Approach 2:
The patent introduces a block dimension to the architecture, organizing pixels into blocks that are then processed by dedicated ADCs. This adds a hierarchical structure (pixels → columns → blocks) that enables parallel processing across blocks while maintaining manageable circuit complexity within each block.
2Productivity
If analog-to-digital conversion is performed in parallel in each column using distributed ADCs, then conversion speed and productivity improve, but device complexity and power consumption increase
Solution Approach 1:
Instead of giving every column its own ADC, the patent segments columns into larger blocks, with each block sharing a dedicated ADC. This reduces the total number of ADCs compared to full parallel architecture while still enabling parallel processing across multiple blocks simultaneously.
Solution Approach 2:
The patent merges multiple columns into blocks that share common ADC resources. Within each block, columns are combined and processed by a shared ADC, reducing overall device complexity and power consumption while maintaining parallel processing capability across different blocks.
3Measurement precision
If a single-slope ADC with ramp generator and counter is used in each column, then measurement precision improves by eliminating clock skew errors, but device complexity and area increase due to distributed counters and comparators
Solution Approach 1:
The patent implements the precise single-slope ADC architecture (with ramp generator and counter) at the block level rather than in every column. Each block has its own ramp generator and counter, eliminating clock skew errors within the block while reducing the total number of these complex components compared to column-level distribution.
Solution Approach 2:
The patent uses dynamic element matching and calibration techniques to maintain high measurement precision across blocks. The system dynamically adjusts for variations between blocks through calibration procedures, achieving consistent accuracy without requiring identical hardware in every block.
4Productivity
If clock frequency is increased to reduce conversion time, then productivity improves, but measurement precision deteriorates due to increased clock skew and noise variations
Solution Approach 1:
By segmenting the array into blocks with dedicated ADCs, the patent allows each block to operate with optimized clock frequencies. This segmentation isolates timing errors to individual blocks, enabling higher overall conversion speeds without propagating clock skew errors across the entire array.
Solution Approach 2:
The patent incorporates calibration mechanisms that use feedback to correct for timing variations and noise. The system measures and compensates for clock skew and noise variations through calibration procedures, enabling high-frequency operation while maintaining measurement precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster, more accurate analog-to-digital conversion with reduced conversion time and power consumption, while being insensitive to clock frequency variations and noise, allowing for higher frequency operation and improved image processing efficiency.
Implementation Method 1
Impinging photons are converted into charges in the pixel array and are accumulated during a certain integration period
Implementation Method 2
The source follower M2 converts the charges stored at the floating diffusion FD into an electrical output voltage signal at the column bus
Data Source
AI summary
An analog-to-digital converter generates an output digital value equivalent to the difference between two analog signals. The converter forms part of a set of converters. The converter receives a first analog signal and a second analog signal (Vreset, Vsig) and a ramp signal (Vramp). A clock is dedicated to the converter, or a sub-set of converters. A control stage enables a first counter based on a comparison of the ramp signal with the first analog signal and the second analog signal. The converter can be calibrated by at least one reference signal (Vref1, Vref2) which is common to the set of converters. A-to-D conversion can include a first A-to-D conversion stage which determines a signal range, selected from a plurality of signal ranges, and a second A-to-D conversion stage which determines an M-bit digital value equivalent to the difference between the first and second analog signals by comparing the signals with a ramp signal, with the ramp signal having the signal range determined by the first analog-to-digital conversion stage.