Pixel Array ADC With Offset-Phase Counters for Faster Conversion
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Solution Overview
Problem
Current analog-to-digital conversion techniques in image sensors face challenges in achieving high conversion speed and resolution due to clock skew and frequency variations between columns, leading to errors and power consumption fluctuations that can affect image quality.
Innovation Solution
The use of multiple counters with offset clock phases allows for increased conversion speed and resolution by enabling subsets of counters during different phases of the ramp signal cycle, maintaining constant power consumption and reducing errors caused by signal level variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single ADC is used in the output stage for time-shared conversion, then device complexity is reduced, but conversion speed becomes a bottleneck
Solution Approach 1:
The patent divides the single ADC function into multiple parallel ADC circuits, each handling a subset of columns. This segmentation enables simultaneous conversion across multiple columns, dramatically increasing conversion speed while keeping each individual ADC circuit relatively simple
2Productivity
If analog-to-digital conversion is performed in parallel in each column, then conversion speed increases, but device complexity increases due to multiple dedicated counters per column
Solution Approach 1:
The patent merges the counter resources by implementing shared counters that can be dynamically allocated to different columns based on phase timing. Instead of dedicating one counter per column, multiple columns share the same counter infrastructure through time-multiplexed access controlled by phase signals
Solution Approach 2:
The patent introduces periodic phase signals that cycle through different columns in a predetermined sequence. Each phase enables a specific subset of counters for a predetermined time period, creating a rhythmic pattern of counter activation that achieves parallel conversion效果 while reusing the same hardware resources
3Productivity
If clock frequency is increased to improve conversion speed, then conversion speed improves, but power consumption increases and causes fluctuations
Solution Approach 1:
The patent uses periodic phase signals to enable counters in a cycling pattern rather than continuously operating all counters at high frequency. Each phase activates a subset of counters for a predetermined time, then deactivates them before activating the next phase, creating periodic operation that reduces average power consumption
Solution Approach 2:
The patent dynamically controls counter activation based on phase timing signals. The counters are enabled and disabled dynamically according to which phase is active, allowing the system to adapt power consumption to the actual conversion needs at different time periods rather than maintaining constant high power operation
4Measurement precision
If multiple counters with offset phases are used, then conversion resolution increases, but device complexity increases
Solution Approach 1:
The patent segments the conversion process into multiple phases, with each phase handling a specific time window of the ramp signal. This segmentation allows the use of multiple counters with offset phases to achieve higher resolution, as each counter captures a portion of the total conversion range during its active phase period
Solution Approach 2:
The phase signals serve multiple functions: they control counter activation timing, determine which counters are active, and coordinate the shared counter resources across different columns. This multi-functionality reduces the need for separate dedicated control circuits for each counter
Data Source
AI summary
An analog-to-digital converter for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input for receiving the first analog signal level and the second analog signal level, an input for receiving a ramp signal and an input for receiving at least one clock signal. A set of N counters, where N≧2, are arranged to use N clock signals which are offset in phase from one another. A control stage is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.