Pixel Array ADC Architecture for Fast TDI Signal Conversion
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Solution Overview
Problem
Current analog-to-digital conversion techniques in imaging sensors face limitations in speed and accuracy due to clock skew and offset noise, particularly in low-light or high-speed imaging applications, where Time Delay and Integration (TDI) methods require separate storage and adder circuits, increasing semiconductor area and layout costs.
Innovation Solution
An analog-to-digital converter architecture that uses a single ramp signal for both analog signals, allowing concurrent or sequential comparison, and employs a control stage with a first counter for integer clock cycles and a second counter for fractional cycles, eliminating the need for direction-changing circuitry and separate adders, and initializes counters with previous exposure values for TDI applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single ADC is used on a time-shared basis for all columns, then device complexity is reduced, but conversion speed and productivity deteriorate
Solution Approach 1:
The patent divides the pixel array into multiple blocks, with each block having its own dedicated ADC. This segmentation allows parallel conversion operations across different blocks, improving overall conversion speed while keeping each individual ADC simple and manageable in complexity.
Solution Approach 2:
The patent introduces a block dimension to the architecture, organizing pixels into blocks where each block has dedicated ADC resources. This adds a spatial dimension to the conversion architecture, enabling parallel processing across blocks while maintaining simplicity within each block.
2Adaptability or versatility
If separate storage registers and adders are provided for TDI, then TDI functionality is enabled, but device complexity and semiconductor area increase
Solution Approach 1:
The patent merges the TDI accumulation function with the ADC counter by allowing the counter to be initialized with a previous exposure value. This eliminates the need for separate storage registers and adders, as the counter itself performs both the analog-to-digital conversion and the digital accumulation of multiple exposures.
Solution Approach 2:
The counter is designed to serve multiple functions: it performs the analog-to-digital conversion by counting clock cycles, stores the digital representation of the current exposure, and accumulates multiple exposure values for TDI applications. This multi-functionality eliminates the need for dedicated separate circuits.
3Measurement precision
If conventional ADC architecture with distributed counters is used, then conversion accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the ramp signal generation and counter control functions into a single centralized unit. This eliminates the complexity of distributing and synchronizing counters across multiple columns, while maintaining conversion accuracy through the centralized control of the ramp signal and counter operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces conversion time, improves accuracy by avoiding clock skew errors, and minimizes semiconductor area by eliminating the need for separate adders, while enabling efficient processing of multiple exposure periods without saturation, particularly beneficial for TDI applications.
Implementation Method 1
Impinging photons are converted into charges in the pixel array
Implementation Method 2
The source follower M2 converts the charges stored at the floating diffusion FD into an electrical output voltage signal at the column bus
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC 30 receives a first analog signal level, a second analog signal level and a ramp signal. A counter 32 is operable to count in a single direction. A control stage is arranged to enable the counter 32 based on a comparison 19 of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a conversion cycle which has two phases, with the ramp signal being reset between the two phases.. The counter 32 can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.