Pixel Array Substrate Bus Line Redistribution for Slim Borders
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Solution Overview
Problem
Conventional gate driver on array (GOA) circuits in display panels have a wide border due to bus lines occupying a significant portion of the circuit width, leading to increased parasitic capacitance and loading, which hinders the achievement of a slim border display panel.
Innovation Solution
The pixel array substrate design includes bus lines on a second surface of the substrate, connected to shift registers on the first surface via conductors, reducing the peripheral area width and minimizing parasitic capacitance by distributing components across both surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bus lines are arranged on the same surface as shift registers in a conventional GOA circuit, then the circuit can be integrated, but the bus lines occupy 40% or more of the whole width, increasing the border width
Solution Approach 1:
The patent applies dimensionality change by moving bus lines from the first surface to the second surface of the substrate. This spatial redistribution across two dimensions (front and back surfaces) reduces the width occupied by bus lines on the first surface from 40% or more to a minimal extent, thereby reducing the border width while maintaining circuit integration
2Quantity of substance
If connection lines cross over bus lines to arrange more lines in limited area, then line density increases, but parasitic capacitance increases and loading of GOA circuit increases
Solution Approach 1:
The patent resolves the line density problem by utilizing the second surface of the substrate for bus lines. This eliminates the need for connection lines to cross over bus lines on the same surface, thereby avoiding the generation of parasitic capacitance while still accommodating the required number of lines through vertical stacking in the third dimension
3Length of stationary object
If bus lines are arranged to minimize width, then border width decreases, but the area available for arranging lines is reduced
Solution Approach 1:
The patent resolves this area constraint by distributing bus lines across the second surface of the substrate. This effectively doubles the available area for line arrangement by utilizing both front and back surfaces, allowing the border width on the first surface to be minimized while maintaining sufficient area for all required connections
Data Source
AI summary
A pixel array substrate including a substrate having at least one via, at least one conductor disposed in the at least one via, pixel units, scan lines electrically connected to the pixel units, at least one shift register and at least one bus line is provided. The pixel units, the scan lines and the at least one shift register are disposed on a first surface of the substrate. The at least one shift register is used to transmit a first gate signal to the corresponding scan lines. The at least one bus line is disposed on a second surface of the substrate. The at least one bus line is electrically connected to the at least one shift register by the at least one conductor.