Pixel Array Storage Capacitor Stacking Aperture Ratio
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Solution Overview
Problem
Conventional in-cell type touch panels have a low aperture ratio due to the placement of storage capacitors and common lines, which decreases the transmittance and increases the thickness of the panel, making them less lightweight, slim, and compact.
Innovation Solution
The storage capacitors are concentrically disposed in one sub-pixel region, and the pixel electrodes are placed in other sub-pixel regions, reducing the overlap with the capacitors and common lines, allowing for a smaller black matrix area and increased aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If storage capacitors and common lines are placed in conventional positions in in-cell touch panels, then the panel structure is simple and manufacturing is easy, but the aperture ratio is low which decreases transmittance and increases thickness
Solution Approach 1:
The patent applies dimensionality change by transitioning from a two-dimensional planar arrangement of storage capacitors to a three-dimensional stacked configuration. The capacitor electrodes are arranged in multiple layers (first capacitor electrode layer, second capacitor electrode layer) with insulating layers in between, allowing capacitors to be positioned vertically above each other rather than only horizontally adjacent. This vertical stacking enables higher aperture ratio while maintaining structural simplicity and manufacturing feasibility.
Solution Approach 2:
The patent implements nesting by placing the first capacitor electrode and second capacitor electrode within the same pixel electrode region, with one capacitor electrode positioned above the other separated by an insulating layer. This nested arrangement allows both capacitor electrodes to occupy the same horizontal footprint area, maximizing the use of available space and increasing the aperture ratio without requiring additional horizontal space that would reduce the light-transmitting area.
2Length of stationary object
If storage capacitors are positioned to overlap pixel electrodes, then the panel can be made thinner and more compact, but the aperture ratio decreases due to increased overlap area requiring larger black matrix
Solution Approach 1:
The patent resolves this contradiction by moving the capacitor structure into the third dimension (vertical stacking). The first and second capacitor electrodes are positioned at different vertical levels with an insulating layer between them, allowing the capacitors to occupy the same horizontal space without increasing the overlap area that would require additional black matrix. This vertical arrangement maintains thin panel profile while preserving high aperture ratio.
3Reliability
If a larger black matrix area is used to shield capacitors and common lines, then the shielding effect is improved, but the aperture ratio is further reduced
Solution Approach 1:
The patent applies nesting by positioning the capacitor electrodes vertically stacked within the pixel electrode region, so that the first capacitor electrode is nested above the second capacitor electrode. This arrangement allows both electrodes to be shielded by the same pixel electrode and black matrix structure, maintaining effective shielding while minimizing the additional black matrix area required. The nested configuration reduces the horizontal footprint of capacitor structures.
Solution Approach 2:
The patent merges the shielding function by having the pixel electrode and black matrix serve dual purposes: they function as display elements while simultaneously providing shielding for the stacked capacitor electrodes. This combined approach eliminates the need for separate shielding structures, maintaining reliability while preserving aperture ratio.
Data Source
AI summary
A pixel array including scan lines, data lines and pixels is provided. The data lines and the scan lines are intersected so as to define sub-pixel regions arranged in array. Each pixel is disposed in a pixel region including (m×n) sub-pixel regions, wherein m is a positive integral and n is a positive integral larger than one. Each pixel includes a plurality of sub-pixels, wherein each sub-pixel includes an active device, a pixel electrode and a storage capacitor. At least a portion of the storage capacitors of the sub-pixels within the same pixel is concentrically disposed in one of the sub-pixel regions.