Pixel Array Bonding Isolation Layout for Higher Chip Yield
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Solution Overview
Problem
The yield loss in semiconductor manufacturing due to randomly distributed defective products and regional variations in epitaxial wafers, leading to inefficiencies in bonding and waste of compound semiconductor epitaxy.
Innovation Solution
A method for manufacturing a pixel array by forming pixel structures at intervals on a native substrate with a bonding isolation layer, optimizing the selection of light-emitting chips based on defective die locations, and performing patterning processes on substrates of various sizes to improve yield and quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a new monocrystalline layer is grown on a carefully prepared single substrate to meet requirements of conductivity type, resistivity, thickness, lattice structure, and integrity, then the quality of the epitaxial layer is improved, but the manufacturing complexity and time consumption increase
Solution Approach 1:
The patent divides the large epitaxial wafer into multiple smaller chip units that can be independently handled and bonded. This segmentation allows the complex epitaxial growth process to be performed once on a large substrate, then the results are divided into manageable portions for assembly, reducing overall manufacturing complexity while maintaining high layer quality.
Solution Approach 2:
The patent performs the complex epitaxial growth process in advance on a large substrate before the final assembly stage. By preparing the high-quality monocrystalline layers beforehand on a carefully prepared single substrate, the demanding growth conditions are met once, and the resulting layers are then distributed across multiple chips, avoiding repetition of the complex process.
2Reliability
If compound semiconductor dies are bonded to CMOS substrate to achieve functional control, then device functionality is improved, but yield loss occurs due to randomly distributed defective products
Solution Approach 1:
The patent segments the large epitaxial wafer into multiple smaller chip units, each containing multiple pixel structures. This allows defective regions to be identified and excluded at the chip level rather than losing entire wafers, thereby maintaining device functionality while improving manufacturing yield by utilizing only defect-free portions.
Solution Approach 2:
The patent applies different treatments to different regions of the epitaxial wafer based on local quality. By mapping defective die locations and excluding only the affected regions from bonding, the patent maintains high functionality in the bonded chips while maximizing yield by utilizing all defect-free areas of the wafer.
3Productivity
If pixel structures are formed at intervals on native substrate with bonding isolation layer, then manufacturing yield is improved, but device complexity increases
Solution Approach 1:
The patent forms pixel structures at intervals rather than continuously, creating discrete bonding units separated by isolation layers. This segmentation improves yield by allowing selective bonding of defect-free regions while the isolation layers prevent defects from propagating between adjacent pixel structures, thereby managing complexity through modular design.
Solution Approach 2:
The bonding isolation layer acts as an intermediary element between adjacent pixel structures. This intermediate layer prevents crosstalk and electrical interference between neighboring structures while allowing each pixel to be independently formed and bonded, improving yield without significantly increasing overall device complexity.
4Productivity
If optimization of light-emitting chip selection based on defective die locations is performed, then manufacturing yield is improved, but measurement and detection difficulty increases
Solution Approach 1:
The patent performs defect detection and mapping of defective die locations before the bonding process. By identifying and recording the locations of defects in advance, the patent can then optimize chip selection to exclude only the affected regions, improving yield while managing detection difficulty through preliminary characterization.
Solution Approach 2:
The patent applies different selection criteria to different regions of the wafer based on local quality assessment. By mapping defective areas and excluding only those specific regions from bonding, the patent improves overall yield while the detection effort is focused only on identifying defect locations rather than examining every potential bonding site in detail.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances manufacturing yield and quality of compound semiconductor chips by optimizing the selection and patterning of pixel arrays, reducing crosstalk and bonding difficulties, and improving light extraction efficiency.
Implementation Method 1
A bonding isolation layer with a multi-layer structure is formed, which is located between adjacent pixel structures distributed along a first direction and covers exposed surfaces of the pixel structures
Implementation Method 2
The pixel structures of a plurality of light-emitting chips are bonded to the bare wafer, with top surfaces of the light-emitting chips facing the bare wafer
Data Source
AI summary
The present disclosure relates to a pixel array and manufacturing method therefor. The method includes providing a bare wafer including a complementary metal oxide semiconductor, providing a native substrate, forming pixel structures arranged at intervals on the native substrate, forming a bonding isolation layer with multi-layer structure. The bonding isolation layer is located between adjacent pixel structures distributed along a first direction and covers the exposed surfaces of the pixel structures to obtain a light-emitting chip. The light-emitting chip includes at least one of the pixel structures distributed along the first direction or a second direction. The first direction is parallel to a top surface of the native substrate, and the second direction is perpendicular to the top surface of the native substrate. The pixel structures of a plurality of the light-emitting chips are bonded to the bare wafer, with top surfaces of the light-emitting chips facing the bare wafer.