Pixel Array Circuit Layout for Uniform Image Sensor Columns
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Solution Overview
Problem
Existing solid-state image capturing devices experience image quality deterioration due to characteristic differences among pixel columns and rows, temperature variations, power supply issues, and color mixture, which are not effectively addressed by current technologies.
Innovation Solution
The device incorporates a pixel array with multiple signal lines connected to circuit groups, where transistors with the same function are arranged adjacently to reduce process variations and temperature differences, and comparators are strategically placed to minimize color mixture, with a stacked-layer structure to uniformize signal line lengths and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If transistors with the same function are arranged in different locations (odd columns below, even columns above), then device complexity is reduced, but characteristic difference among pixel columns increases due to process variation and temperature distribution
Solution Approach 1:
The patent merges transistors with the same function into adjacent locations within the pixel array. Specifically, signal line selection transistors, transfer transistors, and reset transistors are arranged adjacently for each pixel column, regardless of whether they are in odd or even columns. This merging approach ensures that transistors experiencing the same process variation and temperature conditions are grouped together, improving characteristic uniformity while maintaining a compact device structure.
2Area of stationary object
If signal lines are routed to different locations (above or below pixel array), then area utilization is improved, but signal line length variation increases causing interference and image quality deterioration
Solution Approach 1:
The patent transitions from a planar routing approach to a three-dimensional stacked configuration. Memory units are placed in different layers (first memory unit in one layer, second memory unit in another layer), allowing signal lines to be routed vertically through the stack. This dimensional change enables uniform signal line lengths for odd and even pixel columns while efficiently utilizing chip area through vertical stacking.
3Adaptability or versatility
If memory units are placed far apart for different pixel columns, then device layout flexibility is improved, but color mixture increases and operation speed decreases
Solution Approach 1:
The patent implements a nested structure where memory units are integrated within the pixel array region. The first memory unit is nested adjacent to odd pixel columns, and the second memory unit is nested adjacent to even pixel columns, both within the same overall array structure. This nesting approach minimizes the distance between memory units and their corresponding pixel columns, reducing color mixture and improving operation speed while maintaining layout flexibility.
Data Source
AI summary
A device includes a pixel array including a plurality of pixels, a first pixel and a second pixel of the plurality of pixels corresponding to different colors, the first pixel and a third pixel of the plurality of pixels corresponding to a same color, a first circuit group connected to the first pixel, a third circuit group connected to the third pixel, and a first circuit included in the first circuit group, a second circuit, and a third circuit included in the third circuit group and having a function same as a function of the first circuit, the third circuit being arranged between the first circuit and the second circuit in a top view.