Pixel Array Driving Method Preventing Mischarge via Gate Signal Delay

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Solution Overview

Problem

In display technology, particularly in liquid crystal display panels, the integration of gate driving circuits on thin film transistor array substrates (GOA technology) leads to issues like pixel mischarge and abnormal image display due to delays in gate signal switching and incomplete closure of sub-pixel rows.

Innovation Solution

A method for driving a pixel array that involves applying gate signals to adjacent rows of sub-pixels, where the gate signals have an on-state and an off-state. After a specific first duration length of the gate signals applied to the first row are switched from the on-state to the off-state, a selection control signal is applied to the second row to switch the connection states of the data lines with the data signal terminals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If gate driving circuits are integrated on thin film transistor array substrates (GOA technology), then production cost is reduced and narrow frame design is realized, but pixel mischarge and abnormal image display occur due to delays in gate signal switching

Engineering Contradiction:
Improveproduction costVSAvoiddisplay quality
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by introducing a first duration length delay before the selection control signal is applied to the second row of sub-pixels. This delay ensures that the gate signal of the first row has completely switched to the off-state before the second row begins charging, preventing pixel mischarge while maintaining the benefits of GOA technology integration

Inventive Principle:
Principle #10Preliminary action

2Productivity

If gate signals are applied to adjacent rows of sub-pixels without delay, then charging speed is improved, but the first row of sub-pixels may not be completely closed before the second row is charged causing pixel mischarge

Engineering Contradiction:
Improvecharging speedVSAvoidpixel charging accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent performs the required action in advance by delaying the selection control signal for the second row until after the first duration length has elapsed. This ensures the first row's gate signal has completely switched off before the second row charging begins, preventing pixel mischarge while maintaining efficient sequential charging

Inventive Principle:
Principle #10Preliminary action

3Reliability

If a delay is introduced between gate signal switching and selection control signal application, then pixel mischarge is prevented, but display response time increases

Engineering Contradiction:
Improvepixel charging accuracyVSAvoiddisplay response time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent introduces a first duration length delay as a preliminary action to ensure complete gate signal switching before the selection control signal is applied. This minimal delay is necessary to prevent pixel mischarge while maintaining overall display response efficiency through continuous sequential charging of adjacent rows

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12217712B2Method for driving pixel array, device, and display panel
Publication Date: 2025.02.04 FUZHOU BOE OPTOELECTRONICS TECH CO LTD
  • US12217712B2 patent drawing
  • US12217712B2 patent drawing
  • US12217712B2 patent drawing

AI summary

A method for driving a pixel array, a device, and a display panel are provided. The data lines electrically connected to the sub-pixels are electrically connected with data signal terminals through switch modules, respectively. The switch modules receive selection control signals to switch connection states of the data lines with the data signal terminals. The method includes: applying gate signals to a gate line corresponding to the first row of sub-pixels and a gate line corresponding to the second row of sub-pixels, respectively; and during a period of applying the gate signals to the second row of sub-pixels to control the second row of sub-pixels, after a first duration length of the gate signals applied to the first row of sub-pixels being switched from the on-state to the off-state, a selection control signal corresponding to the second row of sub-pixels controlling the switch modules to switch the connection states.